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ARM Remove a bit of dead code.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152061 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-03-05 21:09:58 +00:00
parent 28f08c93e7
commit af9f4bc752
2 changed files with 0 additions and 14 deletions
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9
lib/Target/ARM/ARMInstrNEON.td
View File

@ -89,15 +89,6 @@ def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
let ParserMatchClass = VecListOneDAsmOperand;
}
// Register list of two sequential D registers.
def VecListTwoDAsmOperand : AsmOperandClass {
let Name = "VecListTwoD";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListOperands";
}
def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
let ParserMatchClass = VecListTwoDAsmOperand;
}
// FIXME: Replace all VecListTwoD with VecListDPair
def VecListDPairAsmOperand : AsmOperandClass {
let Name = "VecListDPair";
let ParserMethod = "parseVectorList";

5
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -1085,11 +1085,6 @@ public:
return VectorList.Count == 1;
}
bool isVecListTwoD() const {
if (!isSingleSpacedVectorList()) return false;
return VectorList.Count == 2;
}
bool isVecListDPair() const {
if (!isSingleSpacedVectorList()) return false;
return (ARMMCRegisterClasses[ARM::DPairRegClassID]