6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

Turn loop strength reduction on by default.

Browse Source 
Only run createLowerConstantExpressionsPass for the simple isel.  The DAG
isel has no need for it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22794 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-15 23:47:04 +00:00
parent db25de496c
commit b0096bd19d
1 changed files with 14 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -7,6 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// Top-level implementation for the PowerPC target.
//
//===----------------------------------------------------------------------===//
@ -28,9 +29,6 @@
#include <iostream>
using namespace llvm;
static cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc", cl::Hidden,
cl::desc("Enable LSR for PPC (beta)"));
namespace {
const std::string PPC32ID = "PowerPC/32bit";
@ -67,11 +65,9 @@ bool PowerPCTargetMachine::addPassesToEmitFile(PassManager &PM,
CodeGenFileType FileType) {
if (FileType != TargetMachine::AssemblyFile) return true;
if (EnablePPCLSR) {
PM.add(createLoopStrengthReducePass());
PM.add(createVerifierPass());
PM.add(createCFGSimplificationPass());
}
// Run loop strength reduction before anything else.
PM.add(createLoopStrengthReducePass());
PM.add(createCFGSimplificationPass());
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
@ -82,15 +78,14 @@ bool PowerPCTargetMachine::addPassesToEmitFile(PassManager &PM,
// FIXME: Implement the switch instruction in the instruction selector!
PM.add(createLowerSwitchPass());
PM.add(createLowerConstantExpressionsPass());
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
// Default to pattern ISel
if (PatternISelTriState == 0)
if (PatternISelTriState == 0) {
PM.add(createLowerConstantExpressionsPass());
PM.add(createPPC32ISelSimple(*this));
else
} else
PM.add(createPPC32ISelPattern(*this));
if (PrintMachineCode)
@ -126,10 +121,9 @@ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
// The JIT does not support or need PIC.
PICEnabled = false;
if (EnablePPCLSR) {
PM.add(createLoopStrengthReducePass());
PM.add(createCFGSimplificationPass());
}
// Run loop strength reduction before anything else.
PM.add(createLoopStrengthReducePass());
PM.add(createCFGSimplificationPass());
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
@ -140,16 +134,16 @@ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
// FIXME: Implement the switch instruction in the instruction selector!
PM.add(createLowerSwitchPass());
PM.add(createLowerConstantExpressionsPass());
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
// Default to pattern ISel
if (PatternISelTriState == 0)
if (PatternISelTriState == 0) {
PM.add(createLowerConstantExpressionsPass());
PM.add(createPPC32ISelSimple(TM));
else
} else {
PM.add(createPPC32ISelPattern(TM));
}
PM.add(createRegisterAllocator());
PM.add(createPrologEpilogCodeInserter());