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add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
allowing us to convert ADD over. deletes 160 lines of .td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115897 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
521ff704a1
commit
b046810fe4
@ -708,10 +708,11 @@ class Or4<bits<8> Val> {
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multiclass ArithBinOpEFLAGS<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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string mnemonic, Format RegMRM, Format MemMRM,
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SDNode opnodeflag, SDNode opnode,
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bit CommutableRR> {
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bit CommutableRR, bit ConvertibleToThreeAddress> {
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = CommutableRR in {
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let isCommutable = CommutableRR,
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isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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def #NAME#8rr : BinOpRR<BaseOpc, mnemonic, Xi8 , opnodeflag>;
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def #NAME#16rr : BinOpRR<BaseOpc, mnemonic, Xi16, opnodeflag>;
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def #NAME#32rr : BinOpRR<BaseOpc, mnemonic, Xi32, opnodeflag>;
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@ -728,14 +729,16 @@ multiclass ArithBinOpEFLAGS<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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def #NAME#32rm : BinOpRM<BaseOpc2, mnemonic, Xi32, opnodeflag>;
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def #NAME#64rm : BinOpRM<BaseOpc2, mnemonic, Xi64, opnodeflag>;
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def #NAME#8ri : BinOpRI<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
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def #NAME#16ri : BinOpRI<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
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def #NAME#32ri : BinOpRI<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
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def #NAME#64ri32: BinOpRI<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
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let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
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def #NAME#8ri : BinOpRI<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
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def #NAME#16ri : BinOpRI<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
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def #NAME#32ri : BinOpRI<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
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def #NAME#64ri32: BinOpRI<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
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def #NAME#16ri8 : BinOpRI8<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
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def #NAME#32ri8 : BinOpRI8<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
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def #NAME#64ri8 : BinOpRI8<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
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def #NAME#16ri8 : BinOpRI8<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
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def #NAME#32ri8 : BinOpRI8<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
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def #NAME#64ri8 : BinOpRI8<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
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}
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} // Constraints = "$src1 = $dst"
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def #NAME#8mr : BinOpMR<BaseOpc, mnemonic, Xi8 , opnode>;
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@ -760,180 +763,17 @@ multiclass ArithBinOpEFLAGS<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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}
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defm AND : ArithBinOpEFLAGS<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
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X86and_flag, and, 1>;
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X86and_flag, and, 1, 0>;
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defm OR : ArithBinOpEFLAGS<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
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X86or_flag, or, 1>;
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X86or_flag, or, 1, 0>;
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defm XOR : ArithBinOpEFLAGS<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
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X86xor_flag, xor, 1>;
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X86xor_flag, xor, 1, 0>;
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defm ADD : ArithBinOpEFLAGS<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
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X86add_flag, add, 1, 1>;
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// Arithmetic.
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let Defs = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
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// Register-Register Addition
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def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
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(ins GR8 :$src1, GR8 :$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
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let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
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// Register-Register Addition
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def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
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(ins GR16:$src1, GR16:$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
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GR16:$src2))]>, OpSize;
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def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
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(ins GR32:$src1, GR32:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
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GR32:$src2))]>;
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def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86add_flag GR64:$src1, GR64:$src2))]>;
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} // end isConvertibleToThreeAddress
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} // end isCommutable
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// These are alternate spellings for use by the disassembler, we mark them as
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// code gen only to ensure they aren't matched by the assembler.
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let isCodeGenOnly = 1 in {
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def ADD8rr_alt: I<0x02, MRMSrcReg,
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(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}", []>;
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def ADD16rr_alt: I<0x03, MRMSrcReg,
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
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def ADD32rr_alt: I<0x03, MRMSrcReg,
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}", []>;
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def ADD64rr_alt : RI<0x03, MRMSrcReg,
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(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}", []>;
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}
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// Register-Memory Addition
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def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
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(ins GR8 :$src1, i8mem :$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
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(load addr:$src2)))]>;
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def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
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(ins GR16:$src1, i16mem:$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
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(load addr:$src2)))]>, OpSize;
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def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i32mem:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
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(load addr:$src2)))]>;
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def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86add_flag GR64:$src1, (load addr:$src2)))]>;
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// Register-Integer Addition
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def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, EFLAGS,
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(X86add_flag GR8:$src1, imm:$src2))]>;
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let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
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// Register-Integer Addition
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def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
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(ins GR16:$src1, i16imm:$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
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def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
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(ins GR32:$src1, i32imm:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86add_flag GR32:$src1, imm:$src2))]>;
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def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
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(ins GR16:$src1, i16i8imm:$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
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def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
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(ins GR32:$src1, i32i8imm:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
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def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
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(ins GR64:$src1, i64i8imm:$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
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def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
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(ins GR64:$src1, i64i32imm:$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, EFLAGS,
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(X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
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}
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} // Constraints = "$src1 = $dst"
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// Memory-Register Addition
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def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), GR8:$src2), addr:$dst),
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(implicit EFLAGS)]>;
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def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), GR16:$src2), addr:$dst),
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(implicit EFLAGS)]>, OpSize;
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def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), GR32:$src2), addr:$dst),
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(implicit EFLAGS)]>;
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def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), GR64:$src2), addr:$dst),
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(implicit EFLAGS)]>;
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def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
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"add{b}\t{$src2, $dst|$dst, $src2}",
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[(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
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(implicit EFLAGS)]>;
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def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}",
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[(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
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(implicit EFLAGS)]>, OpSize;
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def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}",
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[(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
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(implicit EFLAGS)]>;
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def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
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(implicit EFLAGS)]>;
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def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
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"add{w}\t{$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), i16immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)]>, OpSize;
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def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
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"add{l}\t{$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), i32immSExt8:$src2),
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addr:$dst),
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(implicit EFLAGS)]>;
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def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
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"add{q}\t{$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
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(implicit EFLAGS)]>;
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// addition to rAX
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def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
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"add{b}\t{$src, %al|%al, $src}", []>;
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def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
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"add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
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"add{l}\t{$src, %eax|%eax, $src}", []>;
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def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src),
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"add{q}\t{$src, %rax|%rax, $src}", []>;
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let Uses = [EFLAGS] in {
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let Constraints = "$src1 = $dst" in {
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@ -1069,7 +909,7 @@ def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src),
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defm SUB : ArithBinOpEFLAGS<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
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X86sub_flag, sub, 0>;
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X86sub_flag, sub, 0, 0>;
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let Uses = [EFLAGS] in {
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