Change ARMInstPrinter::printPredicateOperand() so it will not abort if it

runs into the undefined 15 condition code value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2012-03-01 22:13:02 +00:00
parent dfa27aea12
commit b0578512c7
2 changed files with 22 additions and 1 deletions

View File

@ -692,7 +692,10 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
if (CC != ARMCC::AL)
// Handle the undefined 15 CC value here for printing so we don't abort().
if ((unsigned)CC == 15)
O << "<und>";
else if (CC != ARMCC::AL)
O << ARMCondCodeToString(CC);
}

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@ -0,0 +1,18 @@
# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep und
# rdar://10841671
0xe3 0xbf
0xdf 0xed 0x61 0x3b
0x71 0xee 0xe0 0x1b
0x72 0xee 0xa3 0x2b
0xdf 0xed 0x60 0x0b
# This is test is dealing with a undefined condition code value of 15 in the
# above sequence of junk bytes and not allowing the disassembler to abort on
# printing the final instruction in this list.
#
# ittte al
# vldr d19, [pc, #388]
# vsub.f64 d17, d17, d16
# vadd.f64 d18, d18, d19
# vldr<und> d16, [pc, #384]