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Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
runs into the undefined 15 condition code value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -692,7 +692,10 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
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void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
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if (CC != ARMCC::AL)
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// Handle the undefined 15 CC value here for printing so we don't abort().
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if ((unsigned)CC == 15)
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O << "<und>";
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else if (CC != ARMCC::AL)
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O << ARMCondCodeToString(CC);
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}
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18
test/MC/Disassembler/ARM/invalid-IT-CC15.txt
Normal file
18
test/MC/Disassembler/ARM/invalid-IT-CC15.txt
Normal file
@ -0,0 +1,18 @@
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# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep und
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# rdar://10841671
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0xe3 0xbf
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0xdf 0xed 0x61 0x3b
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0x71 0xee 0xe0 0x1b
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0x72 0xee 0xa3 0x2b
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0xdf 0xed 0x60 0x0b
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# This is test is dealing with a undefined condition code value of 15 in the
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# above sequence of junk bytes and not allowing the disassembler to abort on
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# printing the final instruction in this list.
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#
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# ittte al
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# vldr d19, [pc, #388]
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# vsub.f64 d17, d17, d16
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# vadd.f64 d18, d18, d19
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# vldr<und> d16, [pc, #384]
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