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addrmode2 is gone from these, so no need for the reg0 operand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-10-12 18:11:24 +00:00
parent 9f45754750
commit b0786b33fa
1 changed files with 0 additions and 24 deletions
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24
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -1232,30 +1232,6 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Inst.addOperand(MCOperand::CreateImm(CRd));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
switch (Inst.getOpcode()) {
case ARM::LDC_OPTION:
case ARM::LDCL_OPTION:
case ARM::LDC2_OPTION:
case ARM::LDC2L_OPTION:
case ARM::STC_OPTION:
case ARM::STCL_OPTION:
case ARM::STC2_OPTION:
case ARM::STC2L_OPTION:
case ARM::LDCL_POST:
case ARM::STCL_POST:
case ARM::LDC2L_POST:
case ARM::STC2L_POST:
case ARM::t2LDC_OPTION:
case ARM::t2LDCL_OPTION:
case ARM::t2STC_OPTION:
case ARM::t2STCL_OPTION:
case ARM::t2LDCL_POST:
case ARM::t2STCL_POST:
break;
default:
Inst.addOperand(MCOperand::CreateReg(0));
break;
}
unsigned P = fieldFromInstruction32(Insn, 24, 1);
unsigned W = fieldFromInstruction32(Insn, 21, 1);