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Add checks to make sure we don't create bogus extend nodes, and fix a bug

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where we were doing exactly that which was causing failures on x86 and
alpha.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26284 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
2006-02-18 02:40:58 +00:00
parent 2b15271571
commit b0d04a7dea
2 changed files with 14 additions and 4 deletions
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14
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -665,6 +665,9 @@ SDOperand DAGCombiner::visitADD(SDNode *N) {
// fold (A+(B-A)) -> B
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
return N1.getOperand(0);
//
if (SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand();
return SDOperand();
}
@@ -2297,13 +2300,16 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
// Get a SetCC of the condition
// FIXME: Should probably make sure that setcc is legal if we ever have a
// target where it isn't.
SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
WorkList.push_back(SCC.Val);
SDOperand Temp, SCC;
// cast from setcc result type to select result type
if (AfterLegalize)
if (AfterLegalize) {
SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
else
} else {
SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
}
WorkList.push_back(SCC.Val);
WorkList.push_back(Temp.Val);
// shl setcc result by log2 n2c
return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,