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Enable -soft-float for MIPS.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147541 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-01-04 19:29:11 +00:00
parent 234f8c9ef8
commit b0e7af7797
1 changed files with 10 additions and 7 deletions
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17
lib/Target/Mips/MipsISelLowering.cpp
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@ -92,17 +92,20 @@ MipsTargetLowering(MipsTargetMachine &TM)
// Set up the register classes
addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
if (HasMips64)
addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
// When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat()) {
if (HasMips64)
addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
else
addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
if (!TM.Options.UseSoftFloat) {
addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
// When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat()) {
if (HasMips64)
addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
else
addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
}
}
// Load extented operations for i1 types must be promoted