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Roll out r123609 due to failures on the llvm-x86_64-linux-checks bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123618 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -38,7 +38,8 @@ bool isAllocaPromotable(const AllocaInst *AI);
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/// made to the IR.
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///
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void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
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DominatorTree &DT, AliasSetTracker *AST = 0);
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DominatorTree &DT, DominanceFrontier &DF,
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AliasSetTracker *AST = 0);
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} // End llvm namespace
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@ -152,6 +152,7 @@ namespace {
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// will not alter the CFG, so say so.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<DominatorTree>();
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AU.addRequired<DominanceFrontier>();
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AU.setPreservesCFG();
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}
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};
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@ -179,6 +180,7 @@ char SROA_SSAUp::ID = 0;
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INITIALIZE_PASS_BEGIN(SROA_DF, "scalarrepl",
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"Scalar Replacement of Aggregates (DF)", false, false)
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INITIALIZE_PASS_DEPENDENCY(DominatorTree)
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INITIALIZE_PASS_DEPENDENCY(DominanceFrontier)
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INITIALIZE_PASS_END(SROA_DF, "scalarrepl",
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"Scalar Replacement of Aggregates (DF)", false, false)
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@ -875,8 +877,11 @@ public:
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bool SROA::performPromotion(Function &F) {
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std::vector<AllocaInst*> Allocas;
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DominatorTree *DT = 0;
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if (HasDomFrontiers)
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DominanceFrontier *DF = 0;
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if (HasDomFrontiers) {
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DT = &getAnalysis<DominatorTree>();
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DF = &getAnalysis<DominanceFrontier>();
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}
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BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function
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@ -895,7 +900,7 @@ bool SROA::performPromotion(Function &F) {
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if (Allocas.empty()) break;
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if (HasDomFrontiers)
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PromoteMemToReg(Allocas, *DT);
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PromoteMemToReg(Allocas, *DT, *DF);
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else {
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SSAUpdater SSA;
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for (unsigned i = 0, e = Allocas.size(); i != e; ++i) {
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@ -40,6 +40,7 @@ namespace {
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//
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<DominatorTree>();
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AU.addRequired<DominanceFrontier>();
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AU.setPreservesCFG();
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// This is a cluster of orthogonal Transforms
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AU.addPreserved<UnifyFunctionExitNodes>();
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@ -53,6 +54,7 @@ char PromotePass::ID = 0;
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INITIALIZE_PASS_BEGIN(PromotePass, "mem2reg", "Promote Memory to Register",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(DominatorTree)
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INITIALIZE_PASS_DEPENDENCY(DominanceFrontier)
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INITIALIZE_PASS_END(PromotePass, "mem2reg", "Promote Memory to Register",
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false, false)
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@ -64,6 +66,7 @@ bool PromotePass::runOnFunction(Function &F) {
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bool Changed = false;
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DominatorTree &DT = getAnalysis<DominatorTree>();
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DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
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while (1) {
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Allocas.clear();
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@ -77,7 +80,7 @@ bool PromotePass::runOnFunction(Function &F) {
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if (Allocas.empty()) break;
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PromoteMemToReg(Allocas, DT);
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PromoteMemToReg(Allocas, DT, DF);
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NumPromoted += Allocas.size();
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Changed = true;
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}
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@ -9,19 +9,10 @@
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//
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// This file promotes memory references to be register references. It promotes
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// alloca instructions which only have loads and stores as uses. An alloca is
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// transformed by using iterated dominator frontiers to place PHI nodes, then
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// traversing the function in depth-first order to rewrite loads and stores as
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// appropriate.
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//
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// The algorithm used here is based on:
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//
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// Sreedhar and Gao. A linear time algorithm for placing phi-nodes.
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// In Proceedings of the 22nd ACM SIGPLAN-SIGACT Symposium on Principles of
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// Programming Languages
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// POPL '95. ACM, New York, NY, 62-73.
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//
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// It has been modified to not explicitly use the DJ graph data structure and to
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// directly compute pruned SSA using per-variable liveness information.
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// transformed by using dominator frontiers to place PHI nodes, then traversing
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// the function in depth-first order to rewrite loads and stores as appropriate.
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// This is just the standard SSA construction algorithm to construct "pruned"
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// SSA form.
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//
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//===----------------------------------------------------------------------===//
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@ -44,7 +35,6 @@
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/CFG.h"
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#include <algorithm>
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#include <queue>
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using namespace llvm;
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STATISTIC(NumLocalPromoted, "Number of alloca's promoted within one block");
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@ -189,6 +179,7 @@ namespace {
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///
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std::vector<AllocaInst*> Allocas;
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DominatorTree &DT;
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DominanceFrontier &DF;
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DIFactory *DIF;
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/// AST - An AliasSetTracker object to update. If null, don't update it.
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@ -226,15 +217,12 @@ namespace {
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/// non-determinstic behavior.
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DenseMap<BasicBlock*, unsigned> BBNumbers;
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/// DomLevels - Maps DomTreeNodes to their level in the dominator tree.
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DenseMap<DomTreeNode*, unsigned> DomLevels;
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/// BBNumPreds - Lazily compute the number of predecessors a block has.
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DenseMap<const BasicBlock*, unsigned> BBNumPreds;
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public:
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PromoteMem2Reg(const std::vector<AllocaInst*> &A, DominatorTree &dt,
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AliasSetTracker *ast)
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: Allocas(A), DT(dt), DIF(0), AST(ast) {}
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DominanceFrontier &df, AliasSetTracker *ast)
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: Allocas(A), DT(dt), DF(df), DIF(0), AST(ast) {}
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~PromoteMem2Reg() {
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delete DIF;
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}
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@ -341,7 +329,7 @@ namespace {
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void PromoteMem2Reg::run() {
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Function &F = *DT.getRoot()->getParent();
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Function &F = *DF.getRoot()->getParent();
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if (AST) PointerAllocaValues.resize(Allocas.size());
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AllocaDbgDeclares.resize(Allocas.size());
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@ -435,25 +423,6 @@ void PromoteMem2Reg::run() {
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}
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}
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// If we haven't computed dominator tree levels, do so now.
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if (DomLevels.empty()) {
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SmallVector<DomTreeNode*, 32> Worklist;
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DomTreeNode *Root = DT.getRootNode();
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DomLevels[Root] = 0;
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Worklist.push_back(Root);
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while (!Worklist.empty()) {
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DomTreeNode *Node = Worklist.pop_back_val();
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unsigned ChildLevel = DomLevels[Node] + 1;
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for (DomTreeNode::iterator CI = Node->begin(), CE = Node->end();
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CI != CE; ++CI) {
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DomLevels[*CI] = ChildLevel;
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Worklist.push_back(*CI);
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}
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}
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}
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// If we haven't computed a numbering for the BB's in the function, do so
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// now.
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if (BBNumbers.empty()) {
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@ -688,14 +657,6 @@ ComputeLiveInBlocks(AllocaInst *AI, AllocaInfo &Info,
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}
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}
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typedef std::pair<DomTreeNode*, unsigned> DomTreeNodePair;
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struct DomTreeNodeCompare {
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bool operator()(const DomTreeNodePair &LHS, const DomTreeNodePair &RHS) {
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return LHS.second <= RHS.second;
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}
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};
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/// DetermineInsertionPoint - At this point, we're committed to promoting the
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/// alloca using IDF's, and the standard SSA construction algorithm. Determine
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/// which blocks need phi nodes and see if we can optimize out some work by
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@ -712,77 +673,46 @@ void PromoteMem2Reg::DetermineInsertionPoint(AllocaInst *AI, unsigned AllocaNum,
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SmallPtrSet<BasicBlock*, 32> LiveInBlocks;
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ComputeLiveInBlocks(AI, Info, DefBlocks, LiveInBlocks);
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// Use a priority queue keyed on dominator tree level so that inserted nodes
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// are handled from the bottom of the dominator tree upwards.
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typedef std::priority_queue<DomTreeNodePair, SmallVector<DomTreeNodePair, 32>,
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DomTreeNodeCompare> IDFPriorityQueue;
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IDFPriorityQueue PQ;
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for (unsigned i = 0, e = Info.DefiningBlocks.size(); i != e; ++i) {
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if (DomTreeNode *Node = DT.getNode(Info.DefiningBlocks[i]))
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PQ.push(std::make_pair(Node, DomLevels[Node]));
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}
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std::vector<std::pair<unsigned, BasicBlock*> > DFBlocks;
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SmallPtrSet<DomTreeNode*, 32> Visited;
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SmallVector<DomTreeNode*, 32> Worklist;
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while (!PQ.empty()) {
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DomTreeNodePair RootPair = PQ.top();
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PQ.pop();
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DomTreeNode *Root = RootPair.first;
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unsigned RootLevel = RootPair.second;
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// Walk all dominator tree children of Root, inspecting their CFG edges with
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// targets elsewhere on the dominator tree. Only targets whose level is at
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// most Root's level are added to the iterated dominance frontier of the
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// definition set.
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Worklist.clear();
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Worklist.push_back(Root);
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while (!Worklist.empty()) {
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DomTreeNode *Node = Worklist.pop_back_val();
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BasicBlock *BB = Node->getBlock();
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for (succ_iterator SI = succ_begin(BB), SE = succ_end(BB); SI != SE;
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++SI) {
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DomTreeNode *SuccNode = DT.getNode(*SI);
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// Quickly skip all CFG edges that are also dominator tree edges instead
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// of catching them below.
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if (SuccNode->getIDom() == Node)
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continue;
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unsigned SuccLevel = DomLevels[SuccNode];
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if (SuccLevel > RootLevel)
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continue;
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if (!Visited.insert(SuccNode))
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continue;
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BasicBlock *SuccBB = SuccNode->getBlock();
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if (!LiveInBlocks.count(SuccBB))
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continue;
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DFBlocks.push_back(std::make_pair(BBNumbers[SuccBB], SuccBB));
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if (!DefBlocks.count(SuccBB))
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PQ.push(std::make_pair(SuccNode, SuccLevel));
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}
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for (DomTreeNode::iterator CI = Node->begin(), CE = Node->end(); CI != CE;
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++CI) {
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if (!Visited.count(*CI))
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Worklist.push_back(*CI);
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}
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}
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}
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if (DFBlocks.size() > 1)
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std::sort(DFBlocks.begin(), DFBlocks.end());
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// Compute the locations where PhiNodes need to be inserted. Look at the
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// dominance frontier of EACH basic-block we have a write in.
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unsigned CurrentVersion = 0;
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for (unsigned i = 0, e = DFBlocks.size(); i != e; ++i)
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QueuePhiNode(DFBlocks[i].second, AllocaNum, CurrentVersion);
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std::vector<std::pair<unsigned, BasicBlock*> > DFBlocks;
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while (!Info.DefiningBlocks.empty()) {
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BasicBlock *BB = Info.DefiningBlocks.back();
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Info.DefiningBlocks.pop_back();
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// Look up the DF for this write, add it to defining blocks.
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DominanceFrontier::const_iterator it = DF.find(BB);
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if (it == DF.end()) continue;
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const DominanceFrontier::DomSetType &S = it->second;
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// In theory we don't need the indirection through the DFBlocks vector.
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// In practice, the order of calling QueuePhiNode would depend on the
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// (unspecified) ordering of basic blocks in the dominance frontier,
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// which would give PHI nodes non-determinstic subscripts. Fix this by
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// processing blocks in order of the occurance in the function.
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for (DominanceFrontier::DomSetType::const_iterator P = S.begin(),
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PE = S.end(); P != PE; ++P) {
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// If the frontier block is not in the live-in set for the alloca, don't
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// bother processing it.
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if (!LiveInBlocks.count(*P))
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continue;
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DFBlocks.push_back(std::make_pair(BBNumbers[*P], *P));
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}
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// Sort by which the block ordering in the function.
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if (DFBlocks.size() > 1)
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std::sort(DFBlocks.begin(), DFBlocks.end());
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for (unsigned i = 0, e = DFBlocks.size(); i != e; ++i) {
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BasicBlock *BB = DFBlocks[i].second;
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if (QueuePhiNode(BB, AllocaNum, CurrentVersion))
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Info.DefiningBlocks.push_back(BB);
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}
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DFBlocks.clear();
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}
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}
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/// RewriteSingleStoreAlloca - If there is only a single store to this value,
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@ -1110,9 +1040,10 @@ NextIteration:
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/// made to the IR.
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///
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void llvm::PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,
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DominatorTree &DT, AliasSetTracker *AST) {
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DominatorTree &DT, DominanceFrontier &DF,
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AliasSetTracker *AST) {
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// If there is nothing to do, bail out...
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if (Allocas.empty()) return;
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PromoteMem2Reg(Allocas, DT, AST).run();
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PromoteMem2Reg(Allocas, DT, DF, AST).run();
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}
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