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[arm fast-isel] Appease the machine verifier by using the proper register

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classes.
rdar://12719844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168733 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-11-27 22:12:11 +00:00
parent 4b3448b03e
commit b1146a242c
1 changed files with 4 additions and 2 deletions
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6
lib/Target/ARM/ARMFastISel.cpp
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@ -2595,10 +2595,12 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
break; break;
case MVT::i8: case MVT::i8:
if (!Subtarget->hasV6Ops()) return 0; if (!Subtarget->hasV6Ops()) return 0;
if (isZExt) if (isZExt) {
Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB; Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
else } else {
Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
}
break; break;
case MVT::i1: case MVT::i1:
if (isZExt) { if (isZExt) {