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Implement sse4.2 string/text processing instructions:
Add patterns and instruction encoding information. Add custom lowering to deal with hardwired return register of uncertain type (xmm0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79377 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7595,6 +7595,43 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
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return nextMBB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned numArgs, bool memArg) const {
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MachineFunction *F = BB->getParent();
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DebugLoc dl = MI->getDebugLoc();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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unsigned Opc;
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if (memArg) {
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Opc = numArgs == 3 ?
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X86::PCMPISTRM128rm :
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X86::PCMPESTRM128rm;
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} else {
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Opc = numArgs == 3 ?
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X86::PCMPISTRM128rr :
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X86::PCMPESTRM128rr;
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}
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MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
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for (unsigned i = 0; i < numArgs; ++i) {
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MachineOperand &Op = MI->getOperand(i+1);
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if (!(Op.isReg() && Op.isImplicit()))
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MIB.addOperand(Op);
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}
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BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
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.addReg(X86::XMM0);
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F->DeleteMachineInstr(MI);
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return BB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
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MachineInstr *MI,
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@ -7804,6 +7841,17 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return BB;
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}
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// String/text processing lowering.
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case X86::PCMPISTRM128REG:
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return EmitPCMP(MI, BB, 3, false /* in-mem */);
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case X86::PCMPISTRM128MEM:
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return EmitPCMP(MI, BB, 3, true /* in-mem */);
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case X86::PCMPESTRM128REG:
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return EmitPCMP(MI, BB, 5, false /* in mem */);
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case X86::PCMPESTRM128MEM:
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return EmitPCMP(MI, BB, 5, true /* in mem */);
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// Atomic Lowering.
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case X86::ATOMAND32:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
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X86::AND32ri, X86::MOV32rm,
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@ -693,6 +693,14 @@ namespace llvm {
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const Value *DstSV, uint64_t DstSVOff,
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const Value *SrcSV, uint64_t SrcSVOff);
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/// Utility function to emit string processing sse4.2 instructions
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/// that return in xmm0.
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// This takes the instruction to expand, the associated machine basic
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// block, the number of args, and whether or not the second arg is
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// in memory or not.
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MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
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unsigned argNum, bool inMem) const;
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/// Utility function to emit atomic bitwise operations (and, or, xor).
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// It takes the bitwise instruction to expand, the associated machine basic
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// block, and the associated X86 opcodes for reg/reg and reg/imm.
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@ -235,6 +235,11 @@ class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
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// SS42AI = SSE 4.2 instructions with TA prefix
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class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE42]>;
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// X86-64 Instruction templates...
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//
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@ -288,4 +293,3 @@ class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> patter
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: Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
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class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;
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@ -3657,6 +3657,11 @@ def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"movntdqa\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
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//===----------------------------------------------------------------------===//
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// SSE4.2 Instructions
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//===----------------------------------------------------------------------===//
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/// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
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let Constraints = "$src1 = $dst" in {
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multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
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@ -3739,3 +3744,115 @@ let Constraints = "$src1 = $dst" in {
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(int_x86_sse42_crc32_64 GR64:$src1, GR64:$src2))]>,
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OpSize, REX_W;
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}
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// String/text processing instructions.
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let Defs = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
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def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"#PCMPISTRM128rr PSEUDO!",
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[(set VR128:$dst,
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(int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
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imm:$src3))]>, OpSize;
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def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"#PCMPISTRM128rm PSEUDO!",
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[(set VR128:$dst,
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(int_x86_sse42_pcmpistrm128 VR128:$src1,
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(load addr:$src2),
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imm:$src3))]>, OpSize;
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}
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let Defs = [XMM0, EFLAGS] in {
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def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[]>, OpSize;
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def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[]>, OpSize;
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}
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let Defs = [EFLAGS], Uses = [EAX, EDX],
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usesCustomDAGSchedInserter = 1 in {
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def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"#PCMPESTRM128rr PSEUDO!",
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[(set VR128:$dst,
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(int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
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VR128:$src3,
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EDX, imm:$src5))]>, OpSize;
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def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"#PCMPESTRM128rm PSEUDO!",
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[(set VR128:$dst,
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(int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
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(load addr:$src3),
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EDX, imm:$src5))]>, OpSize;
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}
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let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
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def PCMPESTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}",
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[]>, OpSize;
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def PCMPESTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}",
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[]>, OpSize;
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}
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let Defs = [ECX, EFLAGS] in {
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multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
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def rr : SS42AI<0x63, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[(set ECX,
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(IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
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(implicit EFLAGS)]>,
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OpSize;
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def rm : SS42AI<0x63, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[(set ECX,
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(IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
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(implicit EFLAGS)]>,
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OpSize;
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}
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}
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defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
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defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
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defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
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defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
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defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
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defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
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let Defs = [ECX, EFLAGS] in {
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let Uses = [EAX, EDX] in {
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multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
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def rr : SS42AI<0x61, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
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[(set ECX,
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(IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
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(implicit EFLAGS)]>,
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OpSize;
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def rm : SS42AI<0x61, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
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[(set ECX,
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(IntId128 VR128:$src1, EAX, (load addr:$src3),
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EDX, imm:$src5)),
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(implicit EFLAGS)]>,
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OpSize;
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}
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}
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}
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defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
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defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
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defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
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defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
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defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
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defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
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