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The Vm and Vn register fields must be the same for a register-register vmov.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119867 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2010-11-19 23:12:43 +00:00
parent ff96b63d6f
commit b16926940e
1 changed files with 6 additions and 2 deletions
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8
lib/Target/ARM/ARMInstrNEON.td
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@ -3884,9 +3884,13 @@ def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
let neverHasSideEffects = 1 in {
def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []>;
N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
let Vn{4-0} = Vm{4-0};
}
def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []>;
N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
let Vn{4-0} = Vm{4-0};
}
// Pseudo vector move instructions for QQ and QQQQ registers. This should
// be expanded after register allocation is completed.