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Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify

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{?,?,?,?} as op11_8 for VEXTd and VEXTq.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89693 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2009-11-23 20:09:13 +00:00
parent e54a5e88a5
commit b16ed11cb4
2 changed files with 10 additions and 24 deletions
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14
lib/Target/ARM/ARMInstrFormats.td
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@ -1324,20 +1324,6 @@ class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
let Inst{4} = op4;
}
// NEON 3 vector register with immediate. This is only used for VEXT where
// op11_8 represents the starting byte index of the extracted result in the
// concatenation of the operands and is left unspecified.
class N3VImm<bit op24, bit op23, bits<2> op21_20, bit op6, bit op4,
dag oops, dag iops, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, opc, asm, cstr, pattern> {
let Inst{24} = op24;
let Inst{23} = op23;
let Inst{21-20} = op21_20;
let Inst{6} = op6;
let Inst{4} = op4;
}
// NEON VMOVs between scalar and core registers.
class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
dag oops, dag iops, Format f, InstrItinClass itin,

20
lib/Target/ARM/ARMInstrNEON.td
View File

@ -2864,18 +2864,18 @@ def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
// VEXT : Vector Extract
class VEXTd<string OpcodeStr, ValueType Ty>
: N3VImm<0,1,0b11,0,0, (outs DPR:$dst),
(ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
[(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
(Ty DPR:$rhs), imm:$index)))]>;
: N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst),
(ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD,
OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
[(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
(Ty DPR:$rhs), imm:$index)))]>;
class VEXTq<string OpcodeStr, ValueType Ty>
: N3VImm<0,1,0b11,1,0, (outs QPR:$dst),
(ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
[(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
(Ty QPR:$rhs), imm:$index)))]>;
: N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
(ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ,
OpcodeStr, "\t$dst, $lhs, $rhs, $index", "",
[(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
(Ty QPR:$rhs), imm:$index)))]>;
def VEXTd8 : VEXTd<"vext.8", v8i8>;
def VEXTd16 : VEXTd<"vext.16", v4i16>;