mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Use a more table driven approach to handling types. Seems to simplify the
code a bit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4493 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
d5a87f80b7
commit
b1761fc4df
@ -90,6 +90,28 @@ namespace {
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};
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}
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/// getClass - Turn a primitive type into a "class" number which is based on the
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/// size of the type, and whether or not it is floating point.
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///
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static inline unsigned getClass(const Type *Ty) {
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switch (Ty->getPrimitiveID()) {
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case Type::SByteTyID:
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case Type::UByteTyID: return 0; // Byte operands are class #0
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case Type::ShortTyID:
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case Type::UShortTyID: return 1; // Short operands are class #1
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return 2; // Int's and pointers are class #2
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case Type::LongTyID:
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case Type::ULongTyID: return 3; // Longs are class #3
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case Type::FloatTyID: return 4; // Float is class #4
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case Type::DoubleTyID: return 5; // Doubles are class #5
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default:
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assert(0 && "Invalid type to getClass!");
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return 0; // not reached
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}
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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@ -97,26 +119,23 @@ namespace {
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void ISel::copyConstantToRegister(Constant *C, unsigned R) {
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assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
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switch (C->getType()->getPrimitiveID()) {
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case Type::SByteTyID:
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BuildMI(BB, X86::MOVir8, 1, R).addSImm(cast<ConstantSInt>(C)->getValue());
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break;
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case Type::UByteTyID:
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BuildMI(BB, X86::MOVir8, 1, R).addZImm(cast<ConstantUInt>(C)->getValue());
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break;
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case Type::ShortTyID:
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BuildMI(BB, X86::MOVir16, 1, R).addSImm(cast<ConstantSInt>(C)->getValue());
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break;
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case Type::UShortTyID:
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BuildMI(BB, X86::MOVir16, 1, R).addZImm(cast<ConstantUInt>(C)->getValue());
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break;
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case Type::IntTyID:
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BuildMI(BB, X86::MOVir32, 1, R).addSImm(cast<ConstantSInt>(C)->getValue());
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break;
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case Type::UIntTyID:
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BuildMI(BB, X86::MOVir32, 1, R).addZImm(cast<ConstantUInt>(C)->getValue());
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break;
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default: assert(0 && "Type not handled yet!");
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if (C->getType()->isIntegral()) {
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unsigned Class = getClass(C->getType());
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assert(Class != 3 && "Type not handled yet!");
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static const unsigned IntegralOpcodeTab[] = {
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X86::MOVir8, X86::MOVir16, X86::MOVir32
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};
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if (C->getType()->isSigned()) {
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ConstantSInt *CSI = cast<ConstantSInt>(C);
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BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
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} else {
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ConstantUInt *CUI = cast<ConstantUInt>(C);
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BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
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}
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} else {
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assert(0 && "Type not handled yet!");
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}
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}
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@ -143,20 +162,6 @@ void ISel::visitReturnInst(ReturnInst &I) {
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BuildMI(BB, X86::RET, 0);
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}
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/// SimpleLog2 - Compute and return Log2 of the input, valid only for inputs 1,
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/// 2, 4, & 8. Used to convert operand size into dense classes.
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///
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static inline unsigned SimpleLog2(unsigned N) {
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switch (N) {
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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case 8: return 3;
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default: assert(0 && "Invalid operand to SimpleLog2!");
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}
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return 0; // not reached
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}
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/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
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/// for constant immediate shift values, and for constant immediate
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/// shift values equal to 1. Even the general case is sort of special,
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@ -169,7 +174,10 @@ ISel::visitShiftInst (ShiftInst & I)
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unsigned DestReg = getReg (I);
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bool isRightShift = (I.getOpcode () == Instruction::Shr);
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bool isOperandUnsigned = I.getType ()->isUnsigned ();
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unsigned OperandClass = SimpleLog2(I.getType()->getPrimitiveSize());
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unsigned OperandClass = getClass(I.getType());
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if (OperandClass > 2)
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visitInstruction(I); // Can't handle longs yet!
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if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
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{
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@ -177,79 +185,34 @@ ISel::visitShiftInst (ShiftInst & I)
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assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
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unsigned char shAmt = CUI->getValue();
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// This is a shift right (SHR).
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static const unsigned SHRUnsignedConstantOperand[] = {
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X86::SHRir8, X86::SHRir16, X86::SHRir32
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};
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// This is a shift right arithmetic (SAR).
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static const unsigned SHRSignedConstantOperand[] = {
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X86::SARir8, X86::SARir16, X86::SARir32
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};
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// This is a shift left (SHL).
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static const unsigned SHLConstantOperand[] = {
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X86::SHLir8, X86::SHLir16, X86::SHLir32
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};
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const unsigned *OpTab = 0; // Figure out the operand table to use
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if (isRightShift) {
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if (isOperandUnsigned)
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OpTab = SHRUnsignedConstantOperand;
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else
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OpTab = SHRSignedConstantOperand;
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} else {
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// This is a left shift (SHL).
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OpTab = SHLConstantOperand;
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}
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// Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
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if (isRightShift)
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{
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if (isOperandUnsigned)
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{
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// This is a shift right logical (SHR).
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switch (OperandClass)
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{
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case 0:
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BuildMI (BB, X86::SHRir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 1:
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BuildMI (BB, X86::SHRir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SHRir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 3:
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default:
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visitInstruction (I);
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break;
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}
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}
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else
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{
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// This is a shift right arithmetic (SAR).
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switch (OperandClass)
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{
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case 0:
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BuildMI (BB, X86::SARir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 1:
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BuildMI (BB, X86::SARir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SARir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 3:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// This is a left shift (SHL).
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switch (OperandClass)
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{
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case 0:
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BuildMI (BB, X86::SHLir8, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 1:
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BuildMI (BB, X86::SHLir16, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 2:
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BuildMI (BB, X86::SHLir32, 2,
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DestReg).addReg (Op0r).addZImm (shAmt);
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break;
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case 3:
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default:
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visitInstruction (I);
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break;
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}
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}
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BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
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}
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else
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{
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@ -263,79 +226,37 @@ ISel::visitShiftInst (ShiftInst & I)
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unsigned Op1r = getReg (I.getOperand (1));
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// Emit: move cl, shiftAmount (put the shift amount in CL.)
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BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r);
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// This is a shift right (SHR).
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static const unsigned SHRUnsignedOperand[] = {
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X86::SHRrr8, X86::SHRrr16, X86::SHRrr32
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};
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// This is a shift right arithmetic (SAR).
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static const unsigned SHRSignedOperand[] = {
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X86::SARrr8, X86::SARrr16, X86::SARrr32
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};
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// This is a shift left (SHL).
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static const unsigned SHLOperand[] = {
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X86::SHLrr8, X86::SHLrr16, X86::SHLrr32
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};
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// Emit: <insn> reg, cl (shift-by-CL opcode; "rr" form.)
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if (isRightShift)
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{
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if (OperandClass)
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{
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// This is a shift right logical (SHR).
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switch (OperandClass)
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{
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case 0:
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BuildMI (BB, X86::SHRrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 1:
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BuildMI (BB, X86::SHRrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SHRrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 3:
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default:
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visitInstruction (I);
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break;
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}
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}
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else
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{
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// This is a shift right arithmetic (SAR).
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switch (OperandClass)
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{
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case 0:
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BuildMI (BB, X86::SARrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 1:
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BuildMI (BB, X86::SARrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SARrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 3:
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default:
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visitInstruction (I);
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break;
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}
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}
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}
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else
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{
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// This is a left shift (SHL).
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switch (OperandClass)
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{
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case 0:
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BuildMI (BB, X86::SHLrr8, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 1:
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BuildMI (BB, X86::SHLrr16, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 2:
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BuildMI (BB, X86::SHLrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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break;
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case 3:
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default:
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visitInstruction (I);
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break;
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}
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}
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const unsigned *OpTab = 0; // Figure out the operand table to use
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if (isRightShift) {
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if (isOperandUnsigned)
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OpTab = SHRUnsignedOperand;
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else
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OpTab = SHRSignedOperand;
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} else {
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// This is a left shift (SHL).
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OpTab = SHLOperand;
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}
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BuildMI (BB, X86::SHLrr32, 2,
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DestReg).addReg (Op0r).addReg (X86::CL);
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}
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}
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@ -344,25 +265,19 @@ ISel::visitShiftInst (ShiftInst & I)
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void ISel::visitAdd(BinaryOperator &B) {
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unsigned Op0r = getReg(B.getOperand(0)), Op1r = getReg(B.getOperand(1));
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unsigned DestReg = getReg(B);
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unsigned Class = getClass(B.getType());
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switch (B.getType()->getPrimitiveSize()) {
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case 1: // UByte, SByte
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BuildMI(BB, X86::ADDrr8, 2, DestReg).addReg(Op0r).addReg(Op1r);
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break;
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case 2: // UShort, Short
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BuildMI(BB, X86::ADDrr16, 2, DestReg).addReg(Op0r).addReg(Op1r);
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break;
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case 4: // UInt, Int
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BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r);
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break;
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case 8: // ULong, Long
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// Here we have a pair of operands each occupying a pair of registers.
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// We need to do an ADDrr32 of the least-significant pair immediately
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// followed by an ADCrr32 (Add with Carry) of the most-significant pair.
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// I don't know how we are representing these multi-register arguments.
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default:
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visitInstruction(B); // abort
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}
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static const unsigned Opcodes[] = { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32 };
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if (Class >= sizeof(Opcodes)/sizeof(Opcodes[0]))
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visitInstruction(B); // Not handled class yet...
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BuildMI(BB, Opcodes[Class], 2, DestReg).addReg(Op0r).addReg(Op1r);
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// For Longs: Here we have a pair of operands each occupying a pair of
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// registers. We need to do an ADDrr32 of the least-significant pair
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// immediately followed by an ADCrr32 (Add with Carry) of the most-significant
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// pair. I don't know how we are representing these multi-register arguments.
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}
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@ -90,6 +90,28 @@ namespace {
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};
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}
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/// getClass - Turn a primitive type into a "class" number which is based on the
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/// size of the type, and whether or not it is floating point.
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///
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static inline unsigned getClass(const Type *Ty) {
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switch (Ty->getPrimitiveID()) {
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case Type::SByteTyID:
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case Type::UByteTyID: return 0; // Byte operands are class #0
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case Type::ShortTyID:
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case Type::UShortTyID: return 1; // Short operands are class #1
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return 2; // Int's and pointers are class #2
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case Type::LongTyID:
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case Type::ULongTyID: return 3; // Longs are class #3
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case Type::FloatTyID: return 4; // Float is class #4
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case Type::DoubleTyID: return 5; // Doubles are class #5
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default:
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assert(0 && "Invalid type to getClass!");
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return 0; // not reached
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}
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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@ -97,26 +119,23 @@ namespace {
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void ISel::copyConstantToRegister(Constant *C, unsigned R) {
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assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
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switch (C->getType()->getPrimitiveID()) {
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case Type::SByteTyID:
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BuildMI(BB, X86::MOVir8, 1, R).addSImm(cast<ConstantSInt>(C)->getValue());
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break;
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case Type::UByteTyID:
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BuildMI(BB, X86::MOVir8, 1, R).addZImm(cast<ConstantUInt>(C)->getValue());
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break;
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case Type::ShortTyID:
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BuildMI(BB, X86::MOVir16, 1, R).addSImm(cast<ConstantSInt>(C)->getValue());
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break;
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case Type::UShortTyID:
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BuildMI(BB, X86::MOVir16, 1, R).addZImm(cast<ConstantUInt>(C)->getValue());
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break;
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case Type::IntTyID:
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BuildMI(BB, X86::MOVir32, 1, R).addSImm(cast<ConstantSInt>(C)->getValue());
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break;
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case Type::UIntTyID:
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BuildMI(BB, X86::MOVir32, 1, R).addZImm(cast<ConstantUInt>(C)->getValue());
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break;
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default: assert(0 && "Type not handled yet!");
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if (C->getType()->isIntegral()) {
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unsigned Class = getClass(C->getType());
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assert(Class != 3 && "Type not handled yet!");
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static const unsigned IntegralOpcodeTab[] = {
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X86::MOVir8, X86::MOVir16, X86::MOVir32
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};
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if (C->getType()->isSigned()) {
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ConstantSInt *CSI = cast<ConstantSInt>(C);
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BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
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} else {
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ConstantUInt *CUI = cast<ConstantUInt>(C);
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BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
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}
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} else {
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assert(0 && "Type not handled yet!");
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}
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}
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@ -143,20 +162,6 @@ void ISel::visitReturnInst(ReturnInst &I) {
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BuildMI(BB, X86::RET, 0);
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}
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/// SimpleLog2 - Compute and return Log2 of the input, valid only for inputs 1,
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/// 2, 4, & 8. Used to convert operand size into dense classes.
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///
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static inline unsigned SimpleLog2(unsigned N) {
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switch (N) {
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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case 8: return 3;
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default: assert(0 && "Invalid operand to SimpleLog2!");
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}
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return 0; // not reached
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}
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|
||||
/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
|
||||
/// for constant immediate shift values, and for constant immediate
|
||||
/// shift values equal to 1. Even the general case is sort of special,
|
||||
@ -169,7 +174,10 @@ ISel::visitShiftInst (ShiftInst & I)
|
||||
unsigned DestReg = getReg (I);
|
||||
bool isRightShift = (I.getOpcode () == Instruction::Shr);
|
||||
bool isOperandUnsigned = I.getType ()->isUnsigned ();
|
||||
unsigned OperandClass = SimpleLog2(I.getType()->getPrimitiveSize());
|
||||
unsigned OperandClass = getClass(I.getType());
|
||||
|
||||
if (OperandClass > 2)
|
||||
visitInstruction(I); // Can't handle longs yet!
|
||||
|
||||
if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
|
||||
{
|
||||
@ -177,79 +185,34 @@ ISel::visitShiftInst (ShiftInst & I)
|
||||
assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
|
||||
unsigned char shAmt = CUI->getValue();
|
||||
|
||||
// This is a shift right (SHR).
|
||||
static const unsigned SHRUnsignedConstantOperand[] = {
|
||||
X86::SHRir8, X86::SHRir16, X86::SHRir32
|
||||
};
|
||||
|
||||
// This is a shift right arithmetic (SAR).
|
||||
static const unsigned SHRSignedConstantOperand[] = {
|
||||
X86::SARir8, X86::SARir16, X86::SARir32
|
||||
};
|
||||
|
||||
// This is a shift left (SHL).
|
||||
static const unsigned SHLConstantOperand[] = {
|
||||
X86::SHLir8, X86::SHLir16, X86::SHLir32
|
||||
};
|
||||
|
||||
const unsigned *OpTab = 0; // Figure out the operand table to use
|
||||
if (isRightShift) {
|
||||
if (isOperandUnsigned)
|
||||
OpTab = SHRUnsignedConstantOperand;
|
||||
else
|
||||
OpTab = SHRSignedConstantOperand;
|
||||
} else {
|
||||
// This is a left shift (SHL).
|
||||
OpTab = SHLConstantOperand;
|
||||
}
|
||||
|
||||
// Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
|
||||
if (isRightShift)
|
||||
{
|
||||
if (isOperandUnsigned)
|
||||
{
|
||||
// This is a shift right logical (SHR).
|
||||
switch (OperandClass)
|
||||
{
|
||||
case 0:
|
||||
BuildMI (BB, X86::SHRir8, 2,
|
||||
DestReg).addReg (Op0r).addZImm (shAmt);
|
||||
break;
|
||||
case 1:
|
||||
BuildMI (BB, X86::SHRir16, 2,
|
||||
DestReg).addReg (Op0r).addZImm (shAmt);
|
||||
break;
|
||||
case 2:
|
||||
BuildMI (BB, X86::SHRir32, 2,
|
||||
DestReg).addReg (Op0r).addZImm (shAmt);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
visitInstruction (I);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// This is a shift right arithmetic (SAR).
|
||||
switch (OperandClass)
|
||||
{
|
||||
case 0:
|
||||
BuildMI (BB, X86::SARir8, 2,
|
||||
DestReg).addReg (Op0r).addZImm (shAmt);
|
||||
break;
|
||||
case 1:
|
||||
BuildMI (BB, X86::SARir16, 2,
|
||||
DestReg).addReg (Op0r).addZImm (shAmt);
|
||||
break;
|
||||
case 2:
|
||||
BuildMI (BB, X86::SARir32, 2,
|
||||
DestReg).addReg (Op0r).addZImm (shAmt);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
visitInstruction (I);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// This is a left shift (SHL).
|
||||
switch (OperandClass)
|
||||
{
|
||||
case 0:
|
||||
BuildMI (BB, X86::SHLir8, 2,
|
||||
DestReg).addReg (Op0r).addZImm (shAmt);
|
||||
break;
|
||||
case 1:
|
||||
BuildMI (BB, X86::SHLir16, 2,
|
||||
DestReg).addReg (Op0r).addZImm (shAmt);
|
||||
break;
|
||||
case 2:
|
||||
BuildMI (BB, X86::SHLir32, 2,
|
||||
DestReg).addReg (Op0r).addZImm (shAmt);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
visitInstruction (I);
|
||||
break;
|
||||
}
|
||||
}
|
||||
BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -263,79 +226,37 @@ ISel::visitShiftInst (ShiftInst & I)
|
||||
unsigned Op1r = getReg (I.getOperand (1));
|
||||
// Emit: move cl, shiftAmount (put the shift amount in CL.)
|
||||
BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg (Op1r);
|
||||
|
||||
// This is a shift right (SHR).
|
||||
static const unsigned SHRUnsignedOperand[] = {
|
||||
X86::SHRrr8, X86::SHRrr16, X86::SHRrr32
|
||||
};
|
||||
|
||||
// This is a shift right arithmetic (SAR).
|
||||
static const unsigned SHRSignedOperand[] = {
|
||||
X86::SARrr8, X86::SARrr16, X86::SARrr32
|
||||
};
|
||||
|
||||
// This is a shift left (SHL).
|
||||
static const unsigned SHLOperand[] = {
|
||||
X86::SHLrr8, X86::SHLrr16, X86::SHLrr32
|
||||
};
|
||||
|
||||
// Emit: <insn> reg, cl (shift-by-CL opcode; "rr" form.)
|
||||
if (isRightShift)
|
||||
{
|
||||
if (OperandClass)
|
||||
{
|
||||
// This is a shift right logical (SHR).
|
||||
switch (OperandClass)
|
||||
{
|
||||
case 0:
|
||||
BuildMI (BB, X86::SHRrr8, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
break;
|
||||
case 1:
|
||||
BuildMI (BB, X86::SHRrr16, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
break;
|
||||
case 2:
|
||||
BuildMI (BB, X86::SHRrr32, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
visitInstruction (I);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// This is a shift right arithmetic (SAR).
|
||||
switch (OperandClass)
|
||||
{
|
||||
case 0:
|
||||
BuildMI (BB, X86::SARrr8, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
break;
|
||||
case 1:
|
||||
BuildMI (BB, X86::SARrr16, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
break;
|
||||
case 2:
|
||||
BuildMI (BB, X86::SARrr32, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
visitInstruction (I);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// This is a left shift (SHL).
|
||||
switch (OperandClass)
|
||||
{
|
||||
case 0:
|
||||
BuildMI (BB, X86::SHLrr8, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
break;
|
||||
case 1:
|
||||
BuildMI (BB, X86::SHLrr16, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
break;
|
||||
case 2:
|
||||
BuildMI (BB, X86::SHLrr32, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
visitInstruction (I);
|
||||
break;
|
||||
}
|
||||
}
|
||||
const unsigned *OpTab = 0; // Figure out the operand table to use
|
||||
if (isRightShift) {
|
||||
if (isOperandUnsigned)
|
||||
OpTab = SHRUnsignedOperand;
|
||||
else
|
||||
OpTab = SHRSignedOperand;
|
||||
} else {
|
||||
// This is a left shift (SHL).
|
||||
OpTab = SHLOperand;
|
||||
}
|
||||
|
||||
|
||||
BuildMI (BB, X86::SHLrr32, 2,
|
||||
DestReg).addReg (Op0r).addReg (X86::CL);
|
||||
}
|
||||
}
|
||||
|
||||
@ -344,25 +265,19 @@ ISel::visitShiftInst (ShiftInst & I)
|
||||
void ISel::visitAdd(BinaryOperator &B) {
|
||||
unsigned Op0r = getReg(B.getOperand(0)), Op1r = getReg(B.getOperand(1));
|
||||
unsigned DestReg = getReg(B);
|
||||
unsigned Class = getClass(B.getType());
|
||||
|
||||
switch (B.getType()->getPrimitiveSize()) {
|
||||
case 1: // UByte, SByte
|
||||
BuildMI(BB, X86::ADDrr8, 2, DestReg).addReg(Op0r).addReg(Op1r);
|
||||
break;
|
||||
case 2: // UShort, Short
|
||||
BuildMI(BB, X86::ADDrr16, 2, DestReg).addReg(Op0r).addReg(Op1r);
|
||||
break;
|
||||
case 4: // UInt, Int
|
||||
BuildMI(BB, X86::ADDrr32, 2, DestReg).addReg(Op0r).addReg(Op1r);
|
||||
break;
|
||||
case 8: // ULong, Long
|
||||
// Here we have a pair of operands each occupying a pair of registers.
|
||||
// We need to do an ADDrr32 of the least-significant pair immediately
|
||||
// followed by an ADCrr32 (Add with Carry) of the most-significant pair.
|
||||
// I don't know how we are representing these multi-register arguments.
|
||||
default:
|
||||
visitInstruction(B); // abort
|
||||
}
|
||||
static const unsigned Opcodes[] = { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32 };
|
||||
|
||||
if (Class >= sizeof(Opcodes)/sizeof(Opcodes[0]))
|
||||
visitInstruction(B); // Not handled class yet...
|
||||
|
||||
BuildMI(BB, Opcodes[Class], 2, DestReg).addReg(Op0r).addReg(Op1r);
|
||||
|
||||
// For Longs: Here we have a pair of operands each occupying a pair of
|
||||
// registers. We need to do an ADDrr32 of the least-significant pair
|
||||
// immediately followed by an ADCrr32 (Add with Carry) of the most-significant
|
||||
// pair. I don't know how we are representing these multi-register arguments.
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user