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Transfer implicit ops when forming load multiple and return instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-10-22 21:29:58 +00:00
parent 458509476b
commit b179b46cc5
3 changed files with 6 additions and 1 deletions
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4
include/llvm/CodeGen/MachineInstr.h
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@@ -416,6 +416,10 @@ public:
/// ///
bool allDefsAreDead() const; bool allDefsAreDead() const;
/// copyImplicitOps - Copy implicit register operands from specified
/// instruction to this instruction.
void copyImplicitOps(const MachineInstr *MI);
// //
// Debugging support // Debugging support
// //

2
lib/CodeGen/SimpleRegisterCoalescing.cpp
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@@ -680,7 +680,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
RemoveCopyFlag(MO.getReg(), CopyMI); RemoveCopyFlag(MO.getReg(), CopyMI);
} }
TransferImplicitOps(CopyMI, NewMI); NewMI->copyImplicitOps(CopyMI);
li_->ReplaceMachineInstrInMaps(CopyMI, NewMI); li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
CopyMI->eraseFromParent(); CopyMI->eraseFromParent();
ReMatCopies.insert(CopyMI); ReMatCopies.insert(CopyMI);

1
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@@ -1196,6 +1196,7 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
unsigned NewOpc = isThumb2 ? ARM::t2LDM_RET : ARM::LDM_RET; unsigned NewOpc = isThumb2 ? ARM::t2LDM_RET : ARM::LDM_RET;
PrevMI->setDesc(TII->get(NewOpc)); PrevMI->setDesc(TII->get(NewOpc));
MO.setReg(ARM::PC); MO.setReg(ARM::PC);
PrevMI->copyImplicitOps(&*MBBI);
MBB.erase(MBBI); MBB.erase(MBBI);
return true; return true;
} }