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Lower certain build_vectors to insertps instructions
Summary: Vectors built with zeros and elements in the same order as another (source) vector are optimized to be built using a single insertps instruction. Also optimize when we move one element in a vector to a different place in that vector while zeroing out some of the other elements. Further optimizations are possible, described in TODO comments. I will be implementing at least some of them in the near future. Added some tests for different cases where this optimization triggers. Reviewers: nadav, delena, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208271 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Filipe Cabecinhas
parent
52298507e8
commit
b19c087aa7
@ -5437,6 +5437,74 @@ static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
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return V;
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}
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/// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
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static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
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unsigned NonZeros, unsigned NumNonZero,
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unsigned NumZero, SelectionDAG &DAG,
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const X86Subtarget *Subtarget,
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const TargetLowering &TLI) {
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// We know there's at least one non-zero element
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unsigned FirstNonZeroIdx = 0;
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SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
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while (FirstNonZero.getOpcode() == ISD::UNDEF ||
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X86::isZeroNode(FirstNonZero)) {
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++FirstNonZeroIdx;
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FirstNonZero = Op->getOperand(FirstNonZeroIdx);
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}
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if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
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!isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
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return SDValue();
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SDValue V = FirstNonZero.getOperand(0);
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unsigned FirstNonZeroDst = cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
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unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
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unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
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unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
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for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
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SDValue Elem = Op.getOperand(Idx);
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if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
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continue;
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// TODO: What else can be here? Deal with it.
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if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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return SDValue();
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// TODO: Some optimizations are still possible here
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// ex: Getting one element from a vector, and the rest from another.
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if (Elem.getOperand(0) != V)
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return SDValue();
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unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
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if (Dst == Idx)
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++CorrectIdx;
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else if (IncorrectIdx == -1U) {
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IncorrectIdx = Idx;
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IncorrectDst = Dst;
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} else
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// There was already one element with an incorrect index.
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// We can't optimize this case to an insertps.
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return SDValue();
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}
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if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
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SDLoc dl(Op);
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EVT VT = Op.getSimpleValueType();
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unsigned ElementMoveMask = 0;
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if (IncorrectIdx == -1U)
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ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
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else
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ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
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SDValue InsertpsMask = DAG.getIntPtrConstant(
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ElementMoveMask | (~NonZeros & 0xf));
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return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
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}
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return SDValue();
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}
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/// getVShift - Return a vector logical shift node.
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///
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static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
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@ -6187,6 +6255,14 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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if (V.getNode()) return V;
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}
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// If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
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if (EVTBits == 32 && NumElems == 4) {
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SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
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NumZero, DAG, Subtarget, *this);
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if (V.getNode())
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return V;
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}
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// If element VT is == 32 bits, turn it into a number of shuffles.
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SmallVector<SDValue, 8> V(NumElems);
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if (NumElems == 4 && NumZero > 0) {
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@ -320,3 +320,259 @@ define <4 x i32> @insertps_from_load_ins_elt_undef_i32(<4 x i32> %a, i32* %b) {
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%result = shufflevector <4 x i32> %a, <4 x i32> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
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ret <4 x i32> %result
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}
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;;;;;; Shuffles optimizable with a single insertps instruction
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define <4 x float> @shuf_XYZ0(<4 x float> %x, <4 x float> %a) {
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; CHECK-LABEL: shuf_XYZ0:
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; CHECK-NOT: pextrd
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; CHECK-NOT: punpckldq
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; CHECK: insertps $8
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; CHECK: ret
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecext1 = extractelement <4 x float> %x, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
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%vecext3 = extractelement <4 x float> %x, i32 2
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%vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
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%vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
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ret <4 x float> %vecinit5
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}
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define <4 x float> @shuf_XY00(<4 x float> %x, <4 x float> %a) {
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; CHECK-LABEL: shuf_XY00:
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; CHECK-NOT: pextrd
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; CHECK-NOT: punpckldq
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; CHECK: insertps $12
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; CHECK: ret
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecext1 = extractelement <4 x float> %x, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
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%vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
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%vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
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ret <4 x float> %vecinit4
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}
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define <4 x float> @shuf_XYY0(<4 x float> %x, <4 x float> %a) {
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; CHECK-LABEL: shuf_XYY0:
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; CHECK-NOT: pextrd
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; CHECK-NOT: punpckldq
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; CHECK: insertps $104
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; CHECK: ret
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecext1 = extractelement <4 x float> %x, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
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%vecinit4 = insertelement <4 x float> %vecinit2, float %vecext1, i32 2
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%vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
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ret <4 x float> %vecinit5
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}
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define <4 x float> @shuf_XYW0(<4 x float> %x, <4 x float> %a) {
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; CHECK-LABEL: shuf_XYW0:
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; CHECK: insertps $232
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; CHECK: ret
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecext1 = extractelement <4 x float> %x, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
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%vecext2 = extractelement <4 x float> %x, i32 3
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%vecinit3 = insertelement <4 x float> %vecinit2, float %vecext2, i32 2
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%vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
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ret <4 x float> %vecinit4
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}
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define <4 x float> @shuf_W00W(<4 x float> %x, <4 x float> %a) {
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; CHECK-LABEL: shuf_W00W:
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; CHECK-NOT: pextrd
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; CHECK-NOT: punpckldq
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; CHECK: insertps $198
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; CHECK: ret
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%vecext = extractelement <4 x float> %x, i32 3
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit2 = insertelement <4 x float> %vecinit, float 0.0, i32 1
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%vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
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%vecinit4 = insertelement <4 x float> %vecinit3, float %vecext, i32 3
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ret <4 x float> %vecinit4
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}
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define <4 x float> @shuf_X00A(<4 x float> %x, <4 x float> %a) {
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; CHECK-LABEL: shuf_X00A:
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; CHECK-NOT: movaps
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; CHECK-NOT: shufps
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; CHECK: insertps $48
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; CHECK: ret
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
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%vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x float> %vecinit4
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}
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define <4 x float> @shuf_X00X(<4 x float> %x, <4 x float> %a) {
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; CHECK-LABEL: shuf_X00X:
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; CHECK-NOT: movaps
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; CHECK-NOT: shufps
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; CHECK: insertps $48
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; CHECK: ret
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
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%vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x float> %vecinit4
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}
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define <4 x float> @shuf_X0YC(<4 x float> %x, <4 x float> %a) {
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; CHECK-LABEL: shuf_X0YC:
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; CHECK: shufps
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; CHECK-NOT: movhlps
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; CHECK-NOT: shufps
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; CHECK: insertps $176
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; CHECK: ret
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
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%vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
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%vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
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ret <4 x float> %vecinit5
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}
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define <4 x i32> @i32_shuf_XYZ0(<4 x i32> %x, <4 x i32> %a) {
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; CHECK-LABEL: i32_shuf_XYZ0:
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; CHECK-NOT: pextrd
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; CHECK-NOT: punpckldq
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; CHECK: insertps $8
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; CHECK: ret
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%vecext = extractelement <4 x i32> %x, i32 0
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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%vecext1 = extractelement <4 x i32> %x, i32 1
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%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
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%vecext3 = extractelement <4 x i32> %x, i32 2
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%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
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%vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
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ret <4 x i32> %vecinit5
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}
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define <4 x i32> @i32_shuf_XY00(<4 x i32> %x, <4 x i32> %a) {
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; CHECK-LABEL: i32_shuf_XY00:
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; CHECK-NOT: pextrd
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; CHECK-NOT: punpckldq
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; CHECK: insertps $12
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; CHECK: ret
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%vecext = extractelement <4 x i32> %x, i32 0
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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%vecext1 = extractelement <4 x i32> %x, i32 1
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%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
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%vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
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%vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
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ret <4 x i32> %vecinit4
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}
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define <4 x i32> @i32_shuf_XYY0(<4 x i32> %x, <4 x i32> %a) {
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; CHECK-LABEL: i32_shuf_XYY0:
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; CHECK-NOT: pextrd
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; CHECK-NOT: punpckldq
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; CHECK: insertps $104
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; CHECK: ret
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%vecext = extractelement <4 x i32> %x, i32 0
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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%vecext1 = extractelement <4 x i32> %x, i32 1
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%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
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%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext1, i32 2
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%vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
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ret <4 x i32> %vecinit5
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}
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define <4 x i32> @i32_shuf_XYW0(<4 x i32> %x, <4 x i32> %a) {
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; CHECK-LABEL: i32_shuf_XYW0:
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; CHECK-NOT: pextrd
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; CHECK-NOT: punpckldq
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; CHECK: insertps $232
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; CHECK: ret
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%vecext = extractelement <4 x i32> %x, i32 0
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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%vecext1 = extractelement <4 x i32> %x, i32 1
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%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
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%vecext2 = extractelement <4 x i32> %x, i32 3
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%vecinit3 = insertelement <4 x i32> %vecinit2, i32 %vecext2, i32 2
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%vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
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ret <4 x i32> %vecinit4
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}
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define <4 x i32> @i32_shuf_W00W(<4 x i32> %x, <4 x i32> %a) {
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; CHECK-LABEL: i32_shuf_W00W:
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; CHECK-NOT: pextrd
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; CHECK-NOT: punpckldq
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; CHECK: insertps $198
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; CHECK: ret
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%vecext = extractelement <4 x i32> %x, i32 3
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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%vecinit2 = insertelement <4 x i32> %vecinit, i32 0, i32 1
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%vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
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%vecinit4 = insertelement <4 x i32> %vecinit3, i32 %vecext, i32 3
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ret <4 x i32> %vecinit4
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}
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define <4 x i32> @i32_shuf_X00A(<4 x i32> %x, <4 x i32> %a) {
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; CHECK-LABEL: i32_shuf_X00A:
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; CHECK-NOT: movaps
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; CHECK-NOT: shufps
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; CHECK: insertps $48
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; CHECK: ret
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%vecext = extractelement <4 x i32> %x, i32 0
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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%vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
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%vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
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%vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x i32> %vecinit4
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}
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define <4 x i32> @i32_shuf_X00X(<4 x i32> %x, <4 x i32> %a) {
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; CHECK-LABEL: i32_shuf_X00X:
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; CHECK-NOT: movaps
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; CHECK-NOT: shufps
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; CHECK: insertps $48
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; CHECK: ret
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%vecext = extractelement <4 x i32> %x, i32 0
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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%vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
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%vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
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%vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x i32> %vecinit4
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}
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define <4 x i32> @i32_shuf_X0YC(<4 x i32> %x, <4 x i32> %a) {
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; CHECK-LABEL: i32_shuf_X0YC:
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; CHECK: shufps
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; CHECK-NOT: movhlps
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; CHECK-NOT: shufps
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; CHECK: insertps $176
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; CHECK: ret
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%vecext = extractelement <4 x i32> %x, i32 0
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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%vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
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%vecinit3 = shufflevector <4 x i32> %vecinit1, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
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%vecinit5 = shufflevector <4 x i32> %vecinit3, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
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ret <4 x i32> %vecinit5
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}
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;; Test for a bug in the first implementation of LowerBuildVectorv4x32
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define < 4 x float> @test_insertps_no_undef(<4 x float> %x) {
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; CHECK-LABEL: test_insertps_no_undef:
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; CHECK: movaps %xmm0, %xmm1
|
||||
; CHECK-NEXT: insertps $8, %xmm1, %xmm1
|
||||
; CHECK-NEXT: maxps %xmm1, %xmm0
|
||||
; CHECK-NEXT: ret
|
||||
%vecext = extractelement <4 x float> %x, i32 0
|
||||
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
||||
%vecext1 = extractelement <4 x float> %x, i32 1
|
||||
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
|
||||
%vecext3 = extractelement <4 x float> %x, i32 2
|
||||
%vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
|
||||
%vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
|
||||
%mask = fcmp olt <4 x float> %vecinit5, %x
|
||||
%res = select <4 x i1> %mask, <4 x float> %x, <4 x float>%vecinit5
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user