From b1c5f88237a57ec575cd8dcb89a2cfa274f7abb2 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 7 May 2014 13:57:22 +0000 Subject: [PATCH] [mips] Add ISA_ adverbs and start using them instead of AdditionalPredicates overrides Summary: One small functional change. The recently added PAUSE instruction now has the HasStdEnc predicate which was accidentally removed by a Requires<>. Depends on D3640 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3641 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208209 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips.td | 3 +++ lib/Target/Mips/Mips64InstrInfo.td | 15 +++++------ lib/Target/Mips/MipsInstrFPU.td | 41 ++++++++++++++---------------- lib/Target/Mips/MipsInstrInfo.td | 29 ++++++++++++--------- 4 files changed, 46 insertions(+), 42 deletions(-) diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 8bb46884194..6ea6013bc85 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -26,11 +26,14 @@ class PredicateControl { list GPRPredicates = []; // Predicates for the FGR size and layout such as IsFP64bit list FGRPredicates = []; + // Predicates for the instruction group membership such as ISA's and ASE's + list InsnPredicates = []; // Predicates for anything else list AdditionalPredicates = []; list Predicates = !listconcat(EncodingPredicates, GPRPredicates, FGRPredicates, + InsnPredicates, AdditionalPredicates); } diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 9f50f601667..a51c8d0fb4e 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -118,14 +118,13 @@ def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>, SRA_FM<0x3f, 0>; // Rotate Instructions -let AdditionalPredicates = [HasMips64r2] in { - def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, - immZExt6>, SRA_FM<0x3a, 1>; - def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, - SRLV_FM<0x16, 1>; - def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, - SRA_FM<0x3e, 1>; -} +def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, + immZExt6>, + SRA_FM<0x3a, 1>, ISA_MIPS64R2; +def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, + SRLV_FM<0x16, 1>, ISA_MIPS64R2; +def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, + SRA_FM<0x3e, 1>, ISA_MIPS64R2; /// Load and Store Instructions /// aligned diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 0b77027038b..0c8443b635b 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -429,51 +429,48 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, ADDS_FM<0x01, 16>; defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; -let AdditionalPredicates = [HasMips32r2] in { - def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, - MADDS_FM<4, 0>; - def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, - MADDS_FM<5, 0>; -} +def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, + MADDS_FM<4, 0>, ISA_MIPS32R2; +def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, + MADDS_FM<5, 0>, ISA_MIPS32R2; -let AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in { +let AdditionalPredicates = [NoNaNsFPMath] in { def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, - MADDS_FM<6, 0>; + MADDS_FM<6, 0>, ISA_MIPS32R2; def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, - MADDS_FM<7, 0>; + MADDS_FM<7, 0>, ISA_MIPS32R2; } -let FGRPredicates = [NotFP64bit], - AdditionalPredicates = [HasMips32r2] in { +let FGRPredicates = [NotFP64bit] in { def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, - MADDS_FM<4, 1>; + MADDS_FM<4, 1>, ISA_MIPS32R2; def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, - MADDS_FM<5, 1>; + MADDS_FM<5, 1>, ISA_MIPS32R2; } let FGRPredicates = [NotFP64bit], - AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in { + AdditionalPredicates = [NoNaNsFPMath] in { def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, - MADDS_FM<6, 1>; + MADDS_FM<6, 1>, ISA_MIPS32R2; def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, - MADDS_FM<7, 1>; + MADDS_FM<7, 1>, ISA_MIPS32R2; } let FGRPredicates = [IsFP64bit], - AdditionalPredicates = [HasMips32r2], isCodeGenOnly=1 in { + isCodeGenOnly=1 in { def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, - MADDS_FM<4, 1>; + MADDS_FM<4, 1>, ISA_MIPS32R2; def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, - MADDS_FM<5, 1>; + MADDS_FM<5, 1>, ISA_MIPS32R2; } let FGRPredicates = [IsFP64bit], - AdditionalPredicates = [HasMips32r2, NoNaNsFPMath], + AdditionalPredicates = [NoNaNsFPMath], isCodeGenOnly=1 in { def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, - MADDS_FM<6, 1>; + MADDS_FM<6, 1>, ISA_MIPS32R2; def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, - MADDS_FM<7, 1>; + MADDS_FM<7, 1>, ISA_MIPS32R2; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 02c08a40696..033d5174db1 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -194,6 +194,15 @@ def IsLE : Predicate<"Subtarget.isLittle()">; def IsBE : Predicate<"!Subtarget.isLittle()">; def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">; +//===----------------------------------------------------------------------===// +// Mips ISA membership adjectives. +//===----------------------------------------------------------------------===// + +class ISA_MIPS32R2 { list InsnPredicates = [HasMips32r2]; } +class ISA_MIPS64R2 { list InsnPredicates = [HasMips64r2]; } + +//===----------------------------------------------------------------------===// + class MipsPat : Pat, PredicateControl { let EncodingPredicates = [HasStdEnc]; } @@ -825,17 +834,14 @@ class ExtBase { - let AdditionalPredicates = [HasMips32r2]; -} + FrmR, opstr>, ISA_MIPS32R2; class InsBase: InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src), !strconcat(opstr, " $rt, $rs, $pos, $size"), [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))], - NoItinerary, FrmR, opstr> { - let AdditionalPredicates = [HasMips32r2]; + NoItinerary, FrmR, opstr>, ISA_MIPS32R2 { let Constraints = "$src = $rt"; } @@ -1000,12 +1006,11 @@ def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, SRLV_FM<7, 0>; // Rotate Instructions -let AdditionalPredicates = [HasMips32r2] in { - def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, - immZExt5>, SRA_FM<2, 1>; - def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, - SRLV_FM<6, 1>; -} +def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, + immZExt5>, + SRA_FM<2, 1>, ISA_MIPS32R2; +def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, + SRLV_FM<6, 1>, ISA_MIPS32R2; /// Load and Store Instructions /// aligned @@ -1191,7 +1196,7 @@ class Barrier : InstSE<(outs), (ins), asmstr, [], NoItinerary, FrmOther>; def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>; def EHB : Barrier<"ehb">, BARRIER_FM<3>; -def PAUSE : Barrier<"pause">, BARRIER_FM<5>, Requires<[HasMips32r2]>; +def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2; //===----------------------------------------------------------------------===// // Instruction aliases