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[Hexagon] Adding combine ri/ir instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-10 22:23:07 +00:00
parent 3e04c3e253
commit b1fac191b2
2 changed files with 30 additions and 0 deletions
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26
lib/Target/Hexagon/HexagonInstrInfoV4.td
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@ -206,6 +206,32 @@ def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
// ALU32/PERM +
//===----------------------------------------------------------------------===//
// Combine a word and an immediate into a register pair.
let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
opExtentBits = 8 in
class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
: ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
bits<5> Rdd;
bits<5> Rs;
bits<8> s8;
let IClass = 0b0111;
let Inst{27-24} = 0b0011;
let Inst{22-21} = MajOp;
let Inst{20-16} = Rs;
let Inst{13} = 0b1;
let Inst{12-5} = s8;
let Inst{4-0} = Rdd;
}
let opExtendable = 2, isCodeGenOnly = 0 in
def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
"$Rdd = combine($Rs, #$s8)">;
let opExtendable = 1, isCodeGenOnly = 0 in
def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
"$Rdd = combine(#$s8, $Rs)">;
//===----------------------------------------------------------------------===//
// LD +
//===----------------------------------------------------------------------===//

4
test/MC/Disassembler/Hexagon/alu32_perm.txt
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@ -10,6 +10,10 @@
# CHECK: r17 = combine(r31.l, r21.l)
0xb0 0xe2 0x0f 0x7c
# CHECK: r17:16 = combine(#21, #31)
0xb0 0xe2 0x3f 0x73
# CHECK: r17:16 = combine(#21, r31)
0xf0 0xe3 0x15 0x73
# CHECK: r17:16 = combine(r21, #31)
0x10 0xdf 0x15 0xf5
# CHECK: r17:16 = combine(r21, r31)
0xf1 0xc3 0x75 0x73