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[AArch64 NEON] Fix a bug in implementing register copy bwtween FPR16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199978 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -135,9 +135,9 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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} else if (AArch64::FPR16RegClass.contains(DestReg, SrcReg)) {
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// The copy of two FPR16 registers is implemented by the copy of two FPR32
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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unsigned Dst = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_16,
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unsigned Dst = TRI->getMatchingSuperReg(DestReg, AArch64::sub_16,
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&AArch64::FPR32RegClass);
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unsigned Src = TRI->getMatchingSuperReg(DestReg, AArch64::sub_16,
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unsigned Src = TRI->getMatchingSuperReg(SrcReg, AArch64::sub_16,
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&AArch64::FPR32RegClass);
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BuildMI(MBB, I, DL, get(AArch64::FMOVss), Dst)
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.addReg(Src);
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@ -1262,4 +1262,15 @@ entry:
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%vecext1 = extractelement <1 x i64> %y, i32 0
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%vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
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ret <2 x i64> %vecinit2
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}
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}
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declare <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16>, <1 x i16>)
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define <1 x i16> @test_copy_FPR16_FPR16(<1 x i16> %a, <1 x i16> %b) {
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; CHECK-LABEL: test_copy_FPR16_FPR16:
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; CHECK: usqadd h1, h0
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; CHECK-NEXT: fmov s0, s1
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entry:
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%vsqadd2.i = call <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16> %b, <1 x i16> %a)
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ret <1 x i16> %vsqadd2.i
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}
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