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https://github.com/c64scene-ar/llvm-6502.git
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Refactoring of arithmetic instruction classes with unary operator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107116 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
628a79771b
commit
b22dc70a5c
@ -1863,82 +1863,95 @@ let isCommutable = 0 in {
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defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
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}
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// Arithmetic
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/// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
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///
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/// Unop Arithmetic
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/// In addition, we also have a special variant of the scalar form here to
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/// represent the associated intrinsic operation. This form is unlike the
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/// plain scalar form, in that it takes an entire vector (instead of a
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/// scalar) and leaves the top elements undefined.
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///
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/// And, we have a special variant form for a full-vector intrinsic form.
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///
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multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
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SDNode OpNode,
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Intrinsic F32Int,
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Intrinsic V4F32Int,
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bit Commutable = 0> {
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// Scalar operation, reg.
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/// sse1_fp_unop_s - SSE1 unops in scalar form.
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multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F32Int> {
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def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set FR32:$dst, (OpNode FR32:$src))]> {
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let isCommutable = Commutable;
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}
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// Scalar operation, mem.
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[(set FR32:$dst, (OpNode FR32:$src))]>;
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def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
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Requires<[HasSSE1, OptForSize]>;
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// Vector operation, reg.
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def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
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let isCommutable = Commutable;
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}
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// Vector operation, mem.
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def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
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// Intrinsic operation, reg.
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def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (F32Int VR128:$src))]> {
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let isCommutable = Commutable;
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}
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// Intrinsic operation, mem.
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[(set VR128:$dst, (F32Int VR128:$src))]>;
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def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
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!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
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}
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// Vector intrinsic operation, reg
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/// sse1_fp_unop_p - SSE1 unops in scalar form.
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multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic V4F32Int> {
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def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
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def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
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def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V4F32Int VR128:$src))]> {
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let isCommutable = Commutable;
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}
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// Vector intrinsic operation, mem
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[(set VR128:$dst, (V4F32Int VR128:$src))]>;
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def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
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}
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/// sse2_fp_unop_s - SSE2 unops in scalar form.
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multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic F64Int> {
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def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
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[(set FR64:$dst, (OpNode FR64:$src))]>;
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def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
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[(set FR64:$dst, (OpNode (load addr:$src)))]>;
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def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (F64Int VR128:$src))]>;
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def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
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}
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/// sse2_fp_unop_p - SSE2 unops in vector forms.
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multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
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SDNode OpNode, Intrinsic V2F64Int> {
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def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
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def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
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def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V2F64Int VR128:$src))]>;
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def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
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}
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// Square root.
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defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
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int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
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defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
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sse1_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ps>,
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sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
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sse2_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_pd>;
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
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int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
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defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
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int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
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defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
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sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>;
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defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
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sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>;
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// Prefetch intrinsic.
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def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
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@ -2011,77 +2024,6 @@ def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
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// SSE2 Instructions
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//===---------------------------------------------------------------------===//
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// Arithmetic
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/// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
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///
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/// In addition, we also have a special variant of the scalar form here to
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/// represent the associated intrinsic operation. This form is unlike the
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/// plain scalar form, in that it takes an entire vector (instead of a
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/// scalar) and leaves the top elements undefined.
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///
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/// And, we have a special variant form for a full-vector intrinsic form.
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///
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/// These four forms can each have a reg or a mem operand, so there are a
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/// total of eight "instructions".
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///
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multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
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SDNode OpNode,
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Intrinsic F64Int,
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Intrinsic V2F64Int,
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bit Commutable = 0> {
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// Scalar operation, reg.
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def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
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[(set FR64:$dst, (OpNode FR64:$src))]> {
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let isCommutable = Commutable;
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}
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// Scalar operation, mem.
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def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
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[(set FR64:$dst, (OpNode (load addr:$src)))]>;
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// Vector operation, reg.
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def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
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let isCommutable = Commutable;
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}
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// Vector operation, mem.
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def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
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// Intrinsic operation, reg.
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def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (F64Int VR128:$src))]> {
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let isCommutable = Commutable;
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}
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// Intrinsic operation, mem.
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def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
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!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
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// Vector intrinsic operation, reg
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def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V2F64Int VR128:$src))]> {
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let isCommutable = Commutable;
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}
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// Vector intrinsic operation, mem
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def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
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}
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// Square root.
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defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
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int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
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// There is no f64 version of the reciprocal approximation instructions.
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