mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-06 01:24:35 +00:00
Remove -new-coalescer-heuristic. It's not useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81600 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@ -52,11 +52,6 @@ EnableJoining("join-liveintervals",
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cl::desc("Coalesce copies (default=true)"),
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cl::desc("Coalesce copies (default=true)"),
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cl::init(true));
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cl::init(true));
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static cl::opt<bool>
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NewHeuristic("new-coalescer-heuristic",
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cl::desc("Use new coalescer heuristic"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool>
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static cl::opt<bool>
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DisableCrossClassJoin("disable-cross-class-join",
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DisableCrossClassJoin("disable-cross-class-join",
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cl::desc("Avoid coalescing cross register class copies"),
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cl::desc("Avoid coalescing cross register class copies"),
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@ -736,28 +731,6 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
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return true;
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return true;
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}
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}
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/// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
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///
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bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
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unsigned DstReg) const {
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MachineBasicBlock *MBB = CopyMI->getParent();
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const MachineLoop *L = loopInfo->getLoopFor(MBB);
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if (!L)
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return false;
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if (MBB != L->getLoopLatch())
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return false;
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LiveInterval &LI = li_->getInterval(DstReg);
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MachineInstrIndex DefIdx = li_->getInstructionIndex(CopyMI);
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LiveInterval::const_iterator DstLR =
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LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
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if (DstLR == LI.end())
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return false;
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if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0].isPHIIndex())
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return true;
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return false;
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}
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/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
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/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
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/// update the subregister number if it is not zero. If DstReg is a
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/// update the subregister number if it is not zero. If DstReg is a
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/// physical register and the existing subregister number of the def / use
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/// physical register and the existing subregister number of the def / use
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@ -1631,9 +1604,6 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
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unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
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const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
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const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
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unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
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unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
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if (TheCopy.isBackEdge)
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Threshold *= 2; // Favors back edge copies.
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unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
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unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
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float Ratio = 1.0 / Threshold;
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float Ratio = 1.0 / Threshold;
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if (Length > Threshold &&
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if (Length > Threshold &&
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@ -1750,28 +1720,6 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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if (NewRC)
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if (NewRC)
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mri_->setRegClass(DstReg, NewRC);
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mri_->setRegClass(DstReg, NewRC);
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if (NewHeuristic) {
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// Add all copies that define val# in the source interval into the queue.
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for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
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e = ResSrcInt->vni_end(); i != e; ++i) {
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const VNInfo *vni = *i;
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// FIXME: Do isPHIDef and isDefAccurate both need to be tested?
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if (vni->def == MachineInstrIndex() || vni->isUnused() || vni->isPHIDef() ||
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!vni->isDefAccurate())
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continue;
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MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
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unsigned NewSrcReg, NewDstReg, NewSrcSubIdx, NewDstSubIdx;
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if (CopyMI &&
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JoinedCopies.count(CopyMI) == 0 &&
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tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg,
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NewSrcSubIdx, NewDstSubIdx)) {
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unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
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JoinQueue->push(CopyRec(CopyMI, LoopDepth,
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isBackEdgeCopy(CopyMI, DstReg)));
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}
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}
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}
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// Remember to delete the copy instruction.
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// Remember to delete the copy instruction.
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JoinedCopies.insert(CopyMI);
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JoinedCopies.insert(CopyMI);
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@ -2382,25 +2330,6 @@ namespace {
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};
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};
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}
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}
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/// getRepIntervalSize - Returns the size of the interval that represents the
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/// specified register.
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template<class SF>
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unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
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return Rc->getRepIntervalSize(Reg);
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}
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/// CopyRecSort::operator - Join priority queue sorting function.
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///
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bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
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// Inner loops first.
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if (left.LoopDepth > right.LoopDepth)
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return false;
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else if (left.LoopDepth == right.LoopDepth)
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if (left.isBackEdge && !right.isBackEdge)
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return false;
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return true;
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}
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void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
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void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
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std::vector<CopyRec> &TryAgain) {
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std::vector<CopyRec> &TryAgain) {
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DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
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DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
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@ -2408,7 +2337,6 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
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std::vector<CopyRec> VirtCopies;
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std::vector<CopyRec> VirtCopies;
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std::vector<CopyRec> PhysCopies;
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std::vector<CopyRec> PhysCopies;
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std::vector<CopyRec> ImpDefCopies;
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std::vector<CopyRec> ImpDefCopies;
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unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
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for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
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for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
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MII != E;) {
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MII != E;) {
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MachineInstr *Inst = MII++;
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MachineInstr *Inst = MII++;
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@ -2427,20 +2355,13 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
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bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
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bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
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bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
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bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
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if (NewHeuristic) {
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JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
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} else {
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if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
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if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
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ImpDefCopies.push_back(CopyRec(Inst, 0, false));
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ImpDefCopies.push_back(CopyRec(Inst, 0));
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else if (SrcIsPhys || DstIsPhys)
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else if (SrcIsPhys || DstIsPhys)
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PhysCopies.push_back(CopyRec(Inst, 0, false));
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PhysCopies.push_back(CopyRec(Inst, 0));
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else
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else
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VirtCopies.push_back(CopyRec(Inst, 0, false));
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VirtCopies.push_back(CopyRec(Inst, 0));
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}
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}
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}
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if (NewHeuristic)
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return;
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// Try coalescing implicit copies first, followed by copies to / from
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// Try coalescing implicit copies first, followed by copies to / from
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// physical registers, then finally copies from virtual registers to
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// physical registers, then finally copies from virtual registers to
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@ -2471,9 +2392,6 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
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void SimpleRegisterCoalescing::joinIntervals() {
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void SimpleRegisterCoalescing::joinIntervals() {
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DEBUG(errs() << "********** JOINING INTERVALS ***********\n");
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DEBUG(errs() << "********** JOINING INTERVALS ***********\n");
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if (NewHeuristic)
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JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
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std::vector<CopyRec> TryAgainList;
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std::vector<CopyRec> TryAgainList;
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if (loopInfo->empty()) {
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if (loopInfo->empty()) {
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// If there are no loops in the function, join intervals in function order.
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// If there are no loops in the function, join intervals in function order.
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@ -2503,36 +2421,15 @@ void SimpleRegisterCoalescing::joinIntervals() {
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// Joining intervals can allow other intervals to be joined. Iteratively join
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// Joining intervals can allow other intervals to be joined. Iteratively join
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// until we make no progress.
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// until we make no progress.
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if (NewHeuristic) {
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SmallVector<CopyRec, 16> TryAgain;
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bool ProgressMade = true;
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while (ProgressMade) {
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ProgressMade = false;
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while (!JoinQueue->empty()) {
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CopyRec R = JoinQueue->pop();
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bool Again = false;
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bool Success = JoinCopy(R, Again);
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if (Success)
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ProgressMade = true;
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else if (Again)
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TryAgain.push_back(R);
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}
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if (ProgressMade) {
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while (!TryAgain.empty()) {
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JoinQueue->push(TryAgain.back());
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TryAgain.pop_back();
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}
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}
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}
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} else {
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bool ProgressMade = true;
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bool ProgressMade = true;
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while (ProgressMade) {
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while (ProgressMade) {
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ProgressMade = false;
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ProgressMade = false;
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for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
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for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
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CopyRec &TheCopy = TryAgainList[i];
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CopyRec &TheCopy = TryAgainList[i];
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if (TheCopy.MI) {
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if (!TheCopy.MI)
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continue;
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bool Again = false;
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bool Again = false;
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bool Success = JoinCopy(TheCopy, Again);
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bool Success = JoinCopy(TheCopy, Again);
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if (Success || !Again) {
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if (Success || !Again) {
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@ -2542,11 +2439,6 @@ void SimpleRegisterCoalescing::joinIntervals() {
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}
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}
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}
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}
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}
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}
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}
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if (NewHeuristic)
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delete JoinQueue;
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}
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/// Return true if the two specified registers belong to different register
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/// Return true if the two specified registers belong to different register
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/// classes. The registers may be either phys or virt regs.
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/// classes. The registers may be either phys or virt regs.
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@ -18,7 +18,6 @@
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/BitVector.h"
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#include <queue>
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namespace llvm {
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namespace llvm {
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class SimpleRegisterCoalescing;
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class SimpleRegisterCoalescing;
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@ -33,44 +32,8 @@ namespace llvm {
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struct CopyRec {
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struct CopyRec {
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MachineInstr *MI;
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MachineInstr *MI;
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unsigned LoopDepth;
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unsigned LoopDepth;
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bool isBackEdge;
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CopyRec(MachineInstr *mi, unsigned depth)
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CopyRec(MachineInstr *mi, unsigned depth, bool be)
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: MI(mi), LoopDepth(depth) {};
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: MI(mi), LoopDepth(depth), isBackEdge(be) {};
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};
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template<class SF> class JoinPriorityQueue;
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/// CopyRecSort - Sorting function for coalescer queue.
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///
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struct CopyRecSort : public std::binary_function<CopyRec,CopyRec,bool> {
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JoinPriorityQueue<CopyRecSort> *JPQ;
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explicit CopyRecSort(JoinPriorityQueue<CopyRecSort> *jpq) : JPQ(jpq) {}
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CopyRecSort(const CopyRecSort &RHS) : JPQ(RHS.JPQ) {}
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bool operator()(CopyRec left, CopyRec right) const;
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};
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/// JoinQueue - A priority queue of copy instructions the coalescer is
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/// going to process.
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template<class SF>
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class JoinPriorityQueue {
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SimpleRegisterCoalescing *Rc;
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std::priority_queue<CopyRec, std::vector<CopyRec>, SF> Queue;
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public:
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explicit JoinPriorityQueue(SimpleRegisterCoalescing *rc)
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: Rc(rc), Queue(SF(this)) {}
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bool empty() const { return Queue.empty(); }
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void push(CopyRec R) { Queue.push(R); }
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CopyRec pop() {
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if (empty()) return CopyRec(0, 0, false);
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CopyRec R = Queue.top();
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Queue.pop();
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return R;
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}
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// Callbacks to SimpleRegisterCoalescing.
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unsigned getRepIntervalSize(unsigned Reg);
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};
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};
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class SimpleRegisterCoalescing : public MachineFunctionPass,
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class SimpleRegisterCoalescing : public MachineFunctionPass,
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@ -86,10 +49,6 @@ namespace llvm {
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BitVector allocatableRegs_;
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BitVector allocatableRegs_;
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DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
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DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
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/// JoinQueue - A priority queue of copy instructions the coalescer is
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/// going to process.
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JoinPriorityQueue<CopyRecSort> *JoinQueue;
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/// JoinedCopies - Keep track of copies eliminated due to coalescing.
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/// JoinedCopies - Keep track of copies eliminated due to coalescing.
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///
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///
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SmallPtrSet<MachineInstr*, 32> JoinedCopies;
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SmallPtrSet<MachineInstr*, 32> JoinedCopies;
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@ -127,15 +86,6 @@ namespace llvm {
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return false;
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return false;
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};
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};
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/// getRepIntervalSize - Called from join priority queue sorting function.
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/// It returns the size of the interval that represent the given register.
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unsigned getRepIntervalSize(unsigned Reg) {
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if (!li_->hasInterval(Reg))
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return 0;
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return li_->getApproximateInstructionCount(li_->getInterval(Reg)) *
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LiveInterval::InstrSlots::NUM;
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}
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/// print - Implement the dump method.
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* = 0) const;
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virtual void print(raw_ostream &O, const Module* = 0) const;
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@ -257,10 +207,6 @@ namespace llvm {
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bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR,
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bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR,
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unsigned Reg);
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unsigned Reg);
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/// isBackEdgeCopy - Return true if CopyMI is a back edge copy.
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///
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bool isBackEdgeCopy(MachineInstr *CopyMI, unsigned DstReg) const;
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/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
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/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
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/// update the subregister number if it is not zero. If DstReg is a
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/// update the subregister number if it is not zero. If DstReg is a
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/// physical register and the existing subregister number of the def / use
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/// physical register and the existing subregister number of the def / use
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