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Remove outdated README entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105303 91177308-0d34-0410-b5e6-96231b3b80d8
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Eli Friedman
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@ -1,27 +1,5 @@
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//===- README_X86_64.txt - Notes for X86-64 code gen ----------------------===//
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Implement different PIC models? Right now we only support Mac OS X with small
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PIC code model.
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//===---------------------------------------------------------------------===//
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For this:
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extern void xx(void);
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void bar(void) {
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xx();
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}
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gcc compiles to:
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.globl _bar
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_bar:
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jmp _xx
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We need to do the tailcall optimization as well.
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//===---------------------------------------------------------------------===//
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AMD64 Optimization Manual 8.2 has some nice information about optimizing integer
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multiplication by a constant. How much of it applies to Intel's X86-64
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implementation? There are definite trade-offs to consider: latency vs. register
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@ -98,124 +76,6 @@ gcc:
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//===---------------------------------------------------------------------===//
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Vararg function prologue can be further optimized. Currently all XMM registers
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are stored into register save area. Most of them can be eliminated since the
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upper bound of the number of XMM registers used are passed in %al. gcc produces
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something like the following:
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movzbl %al, %edx
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leaq 0(,%rdx,4), %rax
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leaq 4+L2(%rip), %rdx
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leaq 239(%rsp), %rax
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jmp *%rdx
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movaps %xmm7, -15(%rax)
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movaps %xmm6, -31(%rax)
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movaps %xmm5, -47(%rax)
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movaps %xmm4, -63(%rax)
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movaps %xmm3, -79(%rax)
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movaps %xmm2, -95(%rax)
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movaps %xmm1, -111(%rax)
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movaps %xmm0, -127(%rax)
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L2:
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It jumps over the movaps that do not need to be stored. Hard to see this being
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significant as it added 5 instruciton (including a indirect branch) to avoid
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executing 0 to 8 stores in the function prologue.
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Perhaps we can optimize for the common case where no XMM registers are used for
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parameter passing. i.e. is %al == 0 jump over all stores. Or in the case of a
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leaf function where we can determine that no XMM input parameter is need, avoid
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emitting the stores at all.
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//===---------------------------------------------------------------------===//
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AMD64 has a complex calling convention for aggregate passing by value:
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1. If the size of an object is larger than two eightbytes, or in C++, is a non-
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POD structure or union type, or contains unaligned fields, it has class
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MEMORY.
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2. Both eightbytes get initialized to class NO_CLASS.
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3. Each field of an object is classified recursively so that always two fields
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are considered. The resulting class is calculated according to the classes
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of the fields in the eightbyte:
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(a) If both classes are equal, this is the resulting class.
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(b) If one of the classes is NO_CLASS, the resulting class is the other
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class.
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(c) If one of the classes is MEMORY, the result is the MEMORY class.
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(d) If one of the classes is INTEGER, the result is the INTEGER.
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(e) If one of the classes is X87, X87UP, COMPLEX_X87 class, MEMORY is used as
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class.
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(f) Otherwise class SSE is used.
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4. Then a post merger cleanup is done:
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(a) If one of the classes is MEMORY, the whole argument is passed in memory.
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(b) If SSEUP is not preceeded by SSE, it is converted to SSE.
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Currently llvm frontend does not handle this correctly.
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Problem 1:
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typedef struct { int i; double d; } QuadWordS;
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It is currently passed in two i64 integer registers. However, gcc compiled
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callee expects the second element 'd' to be passed in XMM0.
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Problem 2:
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typedef struct { int32_t i; float j; double d; } QuadWordS;
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The size of the first two fields == i64 so they will be combined and passed in
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a integer register RDI. The third field is still passed in XMM0.
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Problem 3:
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typedef struct { int64_t i; int8_t j; int64_t d; } S;
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void test(S s)
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The size of this aggregate is greater than two i64 so it should be passed in
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memory. Currently llvm breaks this down and passed it in three integer
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registers.
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Problem 4:
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Taking problem 3 one step ahead where a function expects a aggregate value
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in memory followed by more parameter(s) passed in register(s).
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void test(S s, int b)
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LLVM IR does not allow parameter passing by aggregates, therefore it must break
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the aggregates value (in problem 3 and 4) into a number of scalar values:
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void %test(long %s.i, byte %s.j, long %s.d);
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However, if the backend were to lower this code literally it would pass the 3
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values in integer registers. To force it be passed in memory, the frontend
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should change the function signiture to:
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void %test(long %undef1, long %undef2, long %undef3, long %undef4,
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long %undef5, long %undef6,
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long %s.i, byte %s.j, long %s.d);
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And the callee would look something like this:
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call void %test( undef, undef, undef, undef, undef, undef,
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%tmp.s.i, %tmp.s.j, %tmp.s.d );
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The first 6 undef parameters would exhaust the 6 integer registers used for
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parameter passing. The following three integer values would then be forced into
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memory.
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For problem 4, the parameter 'd' would be moved to the front of the parameter
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list so it will be passed in register:
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void %test(int %d,
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long %undef1, long %undef2, long %undef3, long %undef4,
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long %undef5, long %undef6,
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long %s.i, byte %s.j, long %s.d);
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//===---------------------------------------------------------------------===//
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Right now the asm printer assumes GlobalAddress are accessed via RIP relative
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addressing. Therefore, it is not possible to generate this:
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movabsq $__ZTV10polynomialIdE+16, %rax
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That is ok for now since we currently only support small model. So the above
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is selected as
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leaq __ZTV10polynomialIdE+16(%rip), %rax
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This is probably slightly slower but is much shorter than movabsq. However, if
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we were to support medium or larger code models, we need to use the movabs
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instruction. We should probably introduce something like AbsoluteAddress to
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distinguish it from GlobalAddress so the asm printer and JIT code emitter can
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do the right thing.
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//===---------------------------------------------------------------------===//
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It's not possible to reference AH, BH, CH, and DH registers in an instruction
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requiring REX prefix. However, divb and mulb both produce results in AH. If isel
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emits a CopyFromReg which gets turned into a movb and that can be allocated a
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