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[NVPTX] Flag surface/texture query instructions with IsTexSurfQuery

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Also, add some tests to make sure we can handle surface/texture
queries on both Fermi and Kepler+.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213268 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski 2014-07-17 14:51:33 +00:00
parent d6663f565c
commit b26ede07ad
2 changed files with 109 additions and 0 deletions
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6
lib/Target/NVPTX/NVPTXIntrinsics.td
View File

@ -4241,6 +4241,8 @@ def SULD_3D_V4I32_ZERO
//-----------------------------------
// Texture Query Intrinsics
//-----------------------------------
let IsSurfTexQuery = 1 in {
def TXQ_CHANNEL_ORDER
: NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
"txq.channel_order.b32 \t$d, [$a];",
@ -4273,6 +4275,7 @@ def TXQ_NUM_MIPMAP_LEVELS
: NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
"txq.num_mipmap_levels.b32 \t$d, [$a];",
[]>;
}
def : Pat<(int_nvvm_txq_channel_order Int64Regs:$a),
(TXQ_CHANNEL_ORDER Int64Regs:$a)>;
@ -4295,6 +4298,8 @@ def : Pat<(int_nvvm_txq_num_mipmap_levels Int64Regs:$a),
//-----------------------------------
// Surface Query Intrinsics
//-----------------------------------
let IsSurfTexQuery = 1 in {
def SUQ_CHANNEL_ORDER
: NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
"suq.channel_order.b32 \t$d, [$a];",
@ -4319,6 +4324,7 @@ def SUQ_ARRAY_SIZE
: NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
"suq.array_size.b32 \t$d, [$a];",
[]>;
}
def : Pat<(int_nvvm_suq_channel_order Int64Regs:$a),
(SUQ_CHANNEL_ORDER Int64Regs:$a)>;

103
test/CodeGen/NVPTX/texsurf-queries.ll Normal file
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@ -0,0 +1,103 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
target triple = "nvptx-unknown-cuda"
@tex0 = internal addrspace(1) global i64 0, align 8
@surf0 = internal addrspace(1) global i64 0, align 8
declare i32 @llvm.nvvm.txq.width(i64)
declare i32 @llvm.nvvm.txq.height(i64)
declare i32 @llvm.nvvm.suq.width(i64)
declare i32 @llvm.nvvm.suq.height(i64)
declare i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)*)
; SM20-LABEL: @t0
; SM30-LABEL: @t0
define i32 @t0(i64 %texHandle) {
; SM20: txq.width.b32
; SM30: txq.width.b32
%width = tail call i32 @llvm.nvvm.txq.width(i64 %texHandle)
ret i32 %width
}
; SM20-LABEL: @t1
; SM30-LABEL: @t1
define i32 @t1() {
; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], tex0
%texHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @tex0)
; SM20: txq.width.b32 %r{{[0-9]+}}, [tex0]
; SM30: txq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
%width = tail call i32 @llvm.nvvm.txq.width(i64 %texHandle)
ret i32 %width
}
; SM20-LABEL: @t2
; SM30-LABEL: @t2
define i32 @t2(i64 %texHandle) {
; SM20: txq.height.b32
; SM30: txq.height.b32
%height = tail call i32 @llvm.nvvm.txq.height(i64 %texHandle)
ret i32 %height
}
; SM20-LABEL: @t3
; SM30-LABEL: @t3
define i32 @t3() {
; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], tex0
%texHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @tex0)
; SM20: txq.height.b32 %r{{[0-9]+}}, [tex0]
; SM30: txq.height.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
%height = tail call i32 @llvm.nvvm.txq.height(i64 %texHandle)
ret i32 %height
}
; SM20-LABEL: @s0
; SM30-LABEL: @s0
define i32 @s0(i64 %surfHandle) {
; SM20: suq.width.b32
; SM30: suq.width.b32
%width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle)
ret i32 %width
}
; SM20-LABEL: @s1
; SM30-LABEL: @s1
define i32 @s1() {
; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], surf0
%surfHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf0)
; SM20: suq.width.b32 %r{{[0-9]+}}, [surf0]
; SM30: suq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
%width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle)
ret i32 %width
}
; SM20-LABEL: @s2
; SM30-LABEL: @s2
define i32 @s2(i64 %surfHandle) {
; SM20: suq.height.b32
; SM30: suq.height.b32
%height = tail call i32 @llvm.nvvm.suq.height(i64 %surfHandle)
ret i32 %height
}
; SM20-LABEL: @s3
; SM30-LABEL: @s3
define i32 @s3() {
; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], surf0
%surfHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf0)
; SM20: suq.height.b32 %r{{[0-9]+}}, [surf0]
; SM30: suq.height.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
%height = tail call i32 @llvm.nvvm.suq.height(i64 %surfHandle)
ret i32 %height
}
!nvvm.annotations = !{!1, !2}
!1 = metadata !{i64 addrspace(1)* @tex0, metadata !"texture", i32 1}
!2 = metadata !{i64 addrspace(1)* @surf0, metadata !"surface", i32 1}