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implement returns of a vector, testcase here: CodeGen/X86/vec_return.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27767 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -449,26 +449,6 @@ X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
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ReturnAddrIndex = 0; // No return address slot generated yet.
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BytesToPopOnReturn = 0; // Callee pops nothing.
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BytesCallerReserves = ArgOffset;
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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default: assert(0 && "Unknown type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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MF.addLiveOut(X86::EAX);
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break;
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case MVT::i64:
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MF.addLiveOut(X86::EAX);
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MF.addLiveOut(X86::EDX);
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break;
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case MVT::f32:
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case MVT::f64:
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MF.addLiveOut(X86::ST0);
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break;
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}
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return ArgValues;
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}
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@ -2676,15 +2656,30 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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default:
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assert(0 && "Do not know how to return this many arguments!");
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abort();
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case 1:
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case 1: // ret void.
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return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
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DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
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case 2: {
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MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
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if (MVT::isInteger(ArgVT))
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if (MVT::isVector(ArgVT)) {
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// Integer or FP vector result -> XMM0.
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if (DAG.getMachineFunction().liveout_empty())
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DAG.getMachineFunction().addLiveOut(X86::XMM0);
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Copy = DAG.getCopyToReg(Op.getOperand(0), X86::XMM0, Op.getOperand(1),
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SDOperand());
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} else if (MVT::isInteger(ArgVT)) {
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// Integer result -> EAX
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if (DAG.getMachineFunction().liveout_empty())
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DAG.getMachineFunction().addLiveOut(X86::EAX);
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Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1),
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SDOperand());
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else if (!X86ScalarSSE) {
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} else if (!X86ScalarSSE) {
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// FP return with fp-stack value.
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if (DAG.getMachineFunction().liveout_empty())
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DAG.getMachineFunction().addLiveOut(X86::ST0);
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std::vector<MVT::ValueType> Tys;
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Tys.push_back(MVT::Other);
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Tys.push_back(MVT::Flag);
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@ -2693,6 +2688,10 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Op.getOperand(1));
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Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
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} else {
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// FP return with ScalarSSE (return on fp-stack).
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if (DAG.getMachineFunction().liveout_empty())
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DAG.getMachineFunction().addLiveOut(X86::ST0);
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SDOperand MemLoc;
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SDOperand Chain = Op.getOperand(0);
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SDOperand Value = Op.getOperand(1);
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@ -2729,6 +2728,11 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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break;
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}
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case 3:
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if (DAG.getMachineFunction().liveout_empty()) {
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DAG.getMachineFunction().addLiveOut(X86::EAX);
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DAG.getMachineFunction().addLiveOut(X86::EDX);
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}
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Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
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SDOperand());
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Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
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