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Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the

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same so we put in the comment field an indicator when we think we are
emitting the 16 bit version. For the direct object emitter, the difference is 
important as well as for other passes which need an accurate count of 
program size. There will be other similar putbacks to this for various
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174747 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2013-02-08 21:42:56 +00:00
parent 089a5f8a8c
commit b2d1275188
3 changed files with 51 additions and 0 deletions
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17
lib/Target/Mips/Mips16InstrInfo.td
View File

@ -31,6 +31,18 @@ def mem16_ea : Operand<i32> {
let EncoderMethod = "getMemEncoding";
}
//
// RI instruction format
//
class F2RI16_ins<bits<5> _op, string asmstr,
InstrItinClass itin>:
FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
!strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
let Constraints = "$rx_ = $rx";
}
//
// Compare a register and immediate and place result in CC
// Implicit use of T8
@ -416,6 +428,10 @@ class MayStore {
//
def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
ArithLogic16Defs<0> {
let AddedComplexity = 5;
}
def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
ArithLogic16Defs<0>;
@ -1055,6 +1071,7 @@ class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
(I CPU16Regs:$in, imm_type:$imm)>;
def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;

4
lib/Target/Mips/MipsInstrInfo.td
View File

@ -299,6 +299,10 @@ def HI16 : SDNodeXForm<imm, [{
return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
}]>;
// Node immediate fits as 16-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
// Node immediate fits as 16-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;

30
test/CodeGen/Mips/addi.ll Normal file
View File

@ -0,0 +1,30 @@
; RUN: llc -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=16
@i = global i32 6, align 4
@j = global i32 12, align 4
@k = global i32 15, align 4
@l = global i32 20, align 4
@.str = private unnamed_addr constant [13 x i8] c"%i %i %i %i\0A\00", align 1
define void @foo() nounwind {
entry:
%0 = load i32* @i, align 4
%add = add nsw i32 %0, 5
store i32 %add, i32* @i, align 4
%1 = load i32* @j, align 4
%sub = sub nsw i32 %1, 5
store i32 %sub, i32* @j, align 4
%2 = load i32* @k, align 4
%add1 = add nsw i32 %2, 10000
store i32 %add1, i32* @k, align 4
%3 = load i32* @l, align 4
%sub2 = sub nsw i32 %3, 10000
store i32 %sub2, i32* @l, align 4
; 16: addiu ${{[0-9]+}}, 5 # 16 bit inst
; 16: addiu ${{[0-9]+}}, -5 # 16 bit inst
; 16: addiu ${{[0-9]+}}, 10000
; 16: addiu ${{[0-9]+}}, -10000
ret void
}