From b2d170d61b4e9af83ddeae30bafbf4505c275a39 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 7 May 2014 12:48:37 +0000 Subject: [PATCH] [mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates No functional change (confirmed by diffing tablegen-erated files). Depends on D3639 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3640 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208201 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips.td | 6 +++++ lib/Target/Mips/MipsCondMov.td | 21 ++++++++--------- lib/Target/Mips/MipsInstrFPU.td | 41 ++++++++++++++++++--------------- 3 files changed, 39 insertions(+), 29 deletions(-) diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 30793e5fb77..8bb46884194 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -22,9 +22,15 @@ include "llvm/Target/Target.td" class PredicateControl { // Predicates for the encoding scheme in use such as HasStdEnc list EncodingPredicates = []; + // Predicates for the GPR size such as IsGP64bit + list GPRPredicates = []; + // Predicates for the FGR size and layout such as IsFP64bit + list FGRPredicates = []; // Predicates for anything else list AdditionalPredicates = []; list Predicates = !listconcat(EncodingPredicates, + GPRPredicates, + FGRPredicates, AdditionalPredicates); } diff --git a/lib/Target/Mips/MipsCondMov.td b/lib/Target/Mips/MipsCondMov.td index 1758eb59d8c..27c201716a6 100644 --- a/lib/Target/Mips/MipsCondMov.td +++ b/lib/Target/Mips/MipsCondMov.td @@ -141,14 +141,14 @@ let isCodeGenOnly = 1 in def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>, CMov_I_F_FM<19, 16>, AdditionalRequires<[IsGP64bit]>; -let AdditionalPredicates = [NotFP64bit] in { +let FGRPredicates = [NotFP64bit] in { def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, II_MOVZ_D>, CMov_I_F_FM<18, 17>; def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, II_MOVN_D>, CMov_I_F_FM<19, 17>; } -let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { +let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>, CMov_I_F_FM<18, 17>; def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>, @@ -180,14 +180,14 @@ def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>, def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>, CMov_F_F_FM<16, 0>; -let AdditionalPredicates = [NotFP64bit] in { +let FGRPredicates = [NotFP64bit] in { def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, MipsCMovFP_T>, CMov_F_F_FM<17, 1>; def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, MipsCMovFP_F>, CMov_F_F_FM<17, 0>; } -let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { +let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>, CMov_F_F_FM<17, 1>; def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>, @@ -198,7 +198,7 @@ let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { defm : MovzPats0; defm : MovzPats1; defm : MovzPats2; -let AdditionalPredicates = [IsGP64bit] in { +let GPRPredicates = [IsGP64bit] in { defm : MovzPats0; defm : MovzPats0; @@ -213,7 +213,7 @@ let AdditionalPredicates = [IsGP64bit] in { } defm : MovnPats; -let AdditionalPredicates = [IsGP64bit] in { +let GPRPredicates = [IsGP64bit] in { defm : MovnPats; defm : MovnPats; defm : MovnPats; @@ -222,19 +222,18 @@ let AdditionalPredicates = [IsGP64bit] in { defm : MovzPats0; defm : MovzPats1; defm : MovnPats; -let AdditionalPredicates = [IsGP64bit] in { - defm : MovzPats0; +let GPRPredicates = [IsGP64bit] in { + defm : MovzPats0; defm : MovzPats1; defm : MovnPats; } -let AdditionalPredicates = [NotFP64bit] in { +let FGRPredicates = [NotFP64bit] in { defm : MovzPats0; defm : MovzPats1; defm : MovnPats; } -let AdditionalPredicates = [IsFP64bit] in { +let FGRPredicates = [IsFP64bit] in { defm : MovzPats0; defm : MovzPats0; diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 9771b390b68..0b77027038b 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -266,7 +266,7 @@ defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>; defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>; defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; -let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { +let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, ABSS_FM<0x8, 16>; def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, @@ -292,7 +292,7 @@ def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, ABSS_FM<0x25, 17>; -let AdditionalPredicates = [NotFP64bit] in { +let FGRPredicates = [NotFP64bit] in { def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, ABSS_FM<0x20, 17>; def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, @@ -301,7 +301,7 @@ let AdditionalPredicates = [NotFP64bit] in { ABSS_FM<0x21, 16>; } -let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { +let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, ABSS_FM<0x20, 17>; def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, @@ -367,12 +367,12 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; -let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { +let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>; def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>; } -let AdditionalPredicates = [NotFP64bit] in { +let FGRPredicates = [NotFP64bit] in { def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>; def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>; } @@ -391,25 +391,26 @@ let AdditionalPredicates = [IsNotNaCl, HasFPIdx] in { def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>; } -let AdditionalPredicates = [NotFP64bit, HasFPIdx, NotInMicroMips, - IsNotNaCl] in { +let FGRPredicates = [NotFP64bit], + AdditionalPredicates = [HasFPIdx, NotInMicroMips, IsNotNaCl] in { def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>; def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>; } -let AdditionalPredicates = [IsFP64bit, HasFPIdx], +let FGRPredicates = [IsFP64bit], AdditionalPredicates = [HasFPIdx], DecoderNamespace="Mips64" in { def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>; def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>; } // Load/store doubleword indexed unaligned. -let AdditionalPredicates = [NotFP64bit, IsNotNaCl] in { +let FGRPredicates = [NotFP64bit], + AdditionalPredicates = [IsNotNaCl] in { def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>; def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>; } -let AdditionalPredicates = [IsFP64bit], DecoderNamespace="Mips64" in { +let FGRPredicates = [IsFP64bit], DecoderNamespace="Mips64" in { def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>; def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>; } @@ -442,28 +443,32 @@ let AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in { MADDS_FM<7, 0>; } -let AdditionalPredicates = [NotFP64bit, HasMips32r2] in { +let FGRPredicates = [NotFP64bit], + AdditionalPredicates = [HasMips32r2] in { def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, MADDS_FM<4, 1>; def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, MADDS_FM<5, 1>; } -let AdditionalPredicates = [NotFP64bit, HasMips32r2, NoNaNsFPMath] in { +let FGRPredicates = [NotFP64bit], + AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in { def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, MADDS_FM<6, 1>; def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, MADDS_FM<7, 1>; } -let AdditionalPredicates = [IsFP64bit, HasMips32r2], isCodeGenOnly=1 in { +let FGRPredicates = [IsFP64bit], + AdditionalPredicates = [HasMips32r2], isCodeGenOnly=1 in { def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, MADDS_FM<4, 1>; def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, MADDS_FM<5, 1>; } -let AdditionalPredicates = [IsFP64bit, HasMips32r2, NoNaNsFPMath], +let FGRPredicates = [IsFP64bit], + AdditionalPredicates = [HasMips32r2, NoNaNsFPMath], isCodeGenOnly=1 in { def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, MADDS_FM<6, 1>; @@ -559,7 +564,7 @@ def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), (TRUNC_W_S FGR32Opnd:$src)>; -let AdditionalPredicates = [NotFP64bit] in { +let FGRPredicates = [NotFP64bit] in { def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), (PseudoCVT_D32_W GPR32Opnd:$src)>; def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), @@ -570,7 +575,7 @@ let AdditionalPredicates = [NotFP64bit] in { (CVT_D32_S FGR32Opnd:$src)>; } -let AdditionalPredicates = [IsFP64bit] in { +let FGRPredicates = [IsFP64bit] in { def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; @@ -599,12 +604,12 @@ let AddedComplexity = 40 in { def : LoadRegImmPat; def : StoreRegImmPat; - let AdditionalPredicates = [IsFP64bit] in { + let FGRPredicates = [IsFP64bit] in { def : LoadRegImmPat; def : StoreRegImmPat; } - let AdditionalPredicates = [NotFP64bit] in { + let FGRPredicates = [NotFP64bit] in { def : LoadRegImmPat; def : StoreRegImmPat; }