6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 18:29:45 +00:00
Code Issues Projects Releases Wiki Activity

MachineRegisterInfo: Make it clear that hints are for vregs

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233986 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2015-04-03 00:18:33 +00:00
parent 7d4d5d39cf
commit b2e4ca21f4
1 changed files with 10 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
include/llvm/CodeGen/MachineRegisterInfo.h
View File

@ -620,22 +620,25 @@ public:
/// setRegAllocationHint - Specify a register allocation hint for the /// setRegAllocationHint - Specify a register allocation hint for the
/// specified virtual register. /// specified virtual register.
void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
RegAllocHints[Reg].first = Type; assert(TargetRegisterInfo::isVirtualRegister(VReg));
RegAllocHints[Reg].second = PrefReg; RegAllocHints[VReg].first = Type;
RegAllocHints[VReg].second = PrefReg;
} }
/// getRegAllocationHint - Return the register allocation hint for the /// getRegAllocationHint - Return the register allocation hint for the
/// specified virtual register. /// specified virtual register.
std::pair<unsigned, unsigned> std::pair<unsigned, unsigned>
getRegAllocationHint(unsigned Reg) const { getRegAllocationHint(unsigned VReg) const {
return RegAllocHints[Reg]; assert(TargetRegisterInfo::isVirtualRegister(VReg));
return RegAllocHints[VReg];
} }
/// getSimpleHint - Return the preferred register allocation hint, or 0 if a /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
/// standard simple hint (Type == 0) is not set. /// standard simple hint (Type == 0) is not set.
unsigned getSimpleHint(unsigned Reg) const { unsigned getSimpleHint(unsigned VReg) const {
std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); assert(TargetRegisterInfo::isVirtualRegister(VReg));
std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
return Hint.first ? 0 : Hint.second; return Hint.first ? 0 : Hint.second;
} }