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enhance X86TypeInfo to include information about the encoding and
operand kind for immediates. Use these to define a new BinOpRI class and switch AND8/16/32ri over to it. AND64ri32 needs some more refactoring before it can make the switcheroo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115752 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -501,6 +501,7 @@ let CodeSize = 2 in {
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/// register class and preferred load to use.
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class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
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PatFrag loadnode, X86MemOperand memoperand,
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ImmType immkind, Operand immoperand,
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bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
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/// VT - This is the value type itself.
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ValueType VT = vt;
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@ -521,6 +522,18 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
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/// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
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X86MemOperand MemOperand = memoperand;
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/// ImmEncoding - This is the encoding of an immediate of this type. For
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/// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
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/// since the immediate fields of i64 instructions is a 32-bit sign extended
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/// value.
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ImmType ImmEncoding = immkind;
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/// ImmOperand - This is the operand kind of an immediate of this type. For
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/// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
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/// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
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/// extended value.
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Operand ImmOperand = immoperand;
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/// HasOddOpcode - This bit is true if the instruction should have an odd (as
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/// opposed to even) opcode. Operations on i8 are usually even, operations on
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/// other datatypes are odd.
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@ -535,10 +548,14 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
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bit HasREX_WPrefix = hasREX_WPrefix;
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}
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def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem , 0, 0, 0>;
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def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem, 1, 1, 0>;
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def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, 1, 0, 0>;
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def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, 1, 0, 1>;
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def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem , Imm8 , i8imm ,
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0, 0, 0>;
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def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem, Imm16, i16imm,
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1, 1, 0>;
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def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, Imm32, i32imm,
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1, 0, 0>;
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def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, Imm32, i64i32imm,
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1, 0, 1>;
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/// ITy - This instruction base class takes the type info for the instruction.
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/// Using this, it:
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@ -548,7 +565,7 @@ def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, 1, 0, 1>;
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/// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
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/// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
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/// or 1 (for i16,i32,i64 operations).
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class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
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class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
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string mnemonic, string args, list<dag> pattern>
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: I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
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opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
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@ -588,6 +605,16 @@ class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
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class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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SDNode opnode, Format f>
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: ITy<opcode, f, typeinfo,
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(outs typeinfo.RegClass:$dst),
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(ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
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mnemonic, "{$src2, $dst|$dst, $src2}",
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[(set typeinfo.RegClass:$dst, EFLAGS,
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(opnode typeinfo.RegClass:$src1, imm:$src2))]> {
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let ImmT = typeinfo.ImmEncoding;
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}
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@ -616,21 +643,10 @@ def AND16rm : BinOpRM<0x22, "and", Xi16, X86and_flag>;
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def AND32rm : BinOpRM<0x22, "and", Xi32, X86and_flag>;
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def AND64rm : BinOpRM<0x22, "and", Xi64, X86and_flag>;
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def AND8ri : Ii8<0x80, MRM4r,
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(outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
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"and{b}\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
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imm:$src2))]>;
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def AND16ri : Ii16<0x81, MRM4r,
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(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"and{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
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imm:$src2))]>, OpSize;
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def AND32ri : Ii32<0x81, MRM4r,
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(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"and{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
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imm:$src2))]>;
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def AND8ri : BinOpRI<0x80, "and", Xi8 , X86and_flag, MRM4r>;
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def AND16ri : BinOpRI<0x80, "and", Xi16, X86and_flag, MRM4r>;
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def AND32ri : BinOpRI<0x80, "and", Xi32, X86and_flag, MRM4r>;
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def AND64ri32 : RIi32<0x81, MRM4r,
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"and{q}\t{$src2, $dst|$dst, $src2}",
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