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https://github.com/c64scene-ar/llvm-6502.git
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R600: Cleanup or test
Fix broken check lines, use multiple check prefixes, add an additional test for i1 or. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227137 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
1d34ec14e9
commit
b33118d503
@ -1,14 +1,13 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; EG-LABEL: {{^}}or_v2i32:
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; FUNC-LABEL: {{^}}or_v2i32:
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-LABEL: {{^}}or_v2i32:
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32> addrspace(1) * %in
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@ -18,18 +17,16 @@ define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in)
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ret void
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}
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; EG-LABEL: {{^}}or_v4i32:
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; FUNC-LABEL: {{^}}or_v4i32:
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-LABEL: {{^}}or_v4i32:
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32> addrspace(1) * %in
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@ -39,7 +36,7 @@ define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in)
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ret void
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}
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; SI-LABEL: {{^}}scalar_or_i32:
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; FUNC-LABEL: {{^}}scalar_or_i32:
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; SI: s_or_b32
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define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%or = or i32 %a, %b
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@ -47,7 +44,7 @@ define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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ret void
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}
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; SI-LABEL: {{^}}vector_or_i32:
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; FUNC-LABEL: {{^}}vector_or_i32:
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; SI: v_or_b32_e32 v{{[0-9]}}
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define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) {
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%loada = load i32 addrspace(1)* %a
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@ -56,7 +53,7 @@ define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b)
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ret void
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}
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; SI-LABEL: {{^}}scalar_or_literal_i32:
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; FUNC-LABEL: {{^}}scalar_or_literal_i32:
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f
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define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
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%or = or i32 %a, 99999
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@ -64,7 +61,7 @@ define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
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ret void
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}
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; SI-LABEL: {{^}}vector_or_literal_i32:
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; FUNC-LABEL: {{^}}vector_or_literal_i32:
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
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define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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%loada = load i32 addrspace(1)* %a, align 4
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@ -73,7 +70,7 @@ define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a,
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ret void
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}
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; SI-LABEL: {{^}}vector_or_inline_immediate_i32:
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; FUNC-LABEL: {{^}}vector_or_inline_immediate_i32:
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; SI: v_or_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
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define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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%loada = load i32 addrspace(1)* %a, align 4
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@ -82,10 +79,10 @@ define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspac
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ret void
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}
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; EG-LABEL: {{^}}scalar_or_i64:
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; FUNC-LABEL: {{^}}scalar_or_i64:
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; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
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; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
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; SI-LABEL: {{^}}scalar_or_i64:
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; SI: s_or_b64
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define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%or = or i64 %a, %b
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@ -93,7 +90,7 @@ define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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ret void
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}
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; SI-LABEL: {{^}}vector_or_i64:
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; FUNC-LABEL: {{^}}vector_or_i64:
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; SI: v_or_b32_e32 v{{[0-9]}}
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; SI: v_or_b32_e32 v{{[0-9]}}
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define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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@ -104,7 +101,7 @@ define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 add
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ret void
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}
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; SI-LABEL: {{^}}scalar_vector_or_i64:
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; FUNC-LABEL: {{^}}scalar_vector_or_i64:
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; SI: v_or_b32_e32 v{{[0-9]}}
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; SI: v_or_b32_e32 v{{[0-9]}}
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define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) {
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@ -114,7 +111,7 @@ define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a,
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ret void
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}
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; SI-LABEL: {{^}}vector_or_i64_loadimm:
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; FUNC-LABEL: {{^}}vector_or_i64_loadimm:
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; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f
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; SI-DAG: s_movk_i32 [[HI_S_IMM:s[0-9]+]], 0x146f
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; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
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@ -129,7 +126,7 @@ define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a,
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}
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; FIXME: The or 0 should really be removed.
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; SI-LABEL: {{^}}vector_or_i64_imm:
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; FUNC-LABEL: {{^}}vector_or_i64_imm:
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; SI: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
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; SI: v_or_b32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]]
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; SI: v_or_b32_e32 {{v[0-9]+}}, 0, {{.*}}
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@ -141,7 +138,7 @@ define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64
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ret void
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}
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; SI-LABEL: {{^}}trunc_i64_or_to_i32:
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; FUNC-LABEL: {{^}}trunc_i64_or_to_i32:
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; SI: s_load_dword s[[SREG0:[0-9]+]]
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; SI: s_load_dword s[[SREG1:[0-9]+]]
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; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]]
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@ -154,14 +151,13 @@ define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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ret void
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}
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; EG-CHECK: {{^}}or_i1:
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; EG-CHECK: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
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; FUNC-LABEL: {{^}}or_i1:
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; EG: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
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; SI-CHECK: {{^}}or_i1:
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; SI-CHECK: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
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; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
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define void @or_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
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%a = load float addrspace(1) * %in0
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%b = load float addrspace(1) * %in1
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%a = load float addrspace(1)* %in0
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%b = load float addrspace(1)* %in1
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%acmp = fcmp oge float %a, 0.000000e+00
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%bcmp = fcmp oge float %b, 0.000000e+00
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%or = or i1 %acmp, %bcmp
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@ -169,3 +165,13 @@ define void @or_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float add
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store float %result, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_or_i1:
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; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], vcc
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define void @s_or_i1(i1 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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%cmp0 = icmp eq i32 %a, %b
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%cmp1 = icmp eq i32 %c, %d
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%or = or i1 %cmp0, %cmp1
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store i1 %or, i1 addrspace(1)* %out
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ret void
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}
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