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Some single-precision VFP instructions can execute in either the VPF or Neon
pipelines, at least on Cortex-A9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129771 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -447,6 +447,10 @@ def VMOVRS : AVConv2I<0b11100001, 0b1010,
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let Inst{6-5} = 0b00;
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let Inst{3-0} = 0b0000;
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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}
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def VMOVSR : AVConv4I<0b11100000, 0b1010,
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@ -464,6 +468,10 @@ def VMOVSR : AVConv4I<0b11100000, 0b1010,
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let Inst{6-5} = 0b00;
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let Inst{3-0} = 0b0000;
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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}
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let neverHasSideEffects = 1 in {
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@ -483,6 +491,10 @@ def VMOVRRD : AVConv3I<0b11000101, 0b1011,
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let Inst{19-16} = Rt2;
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let Inst{7-6} = 0b00;
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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}
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def VMOVRRS : AVConv3I<0b11000101, 0b1010,
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@ -490,6 +502,10 @@ def VMOVRRS : AVConv3I<0b11000101, 0b1010,
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IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{7-6} = 0b00;
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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}
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} // neverHasSideEffects
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@ -512,6 +528,10 @@ def VMOVDRR : AVConv5I<0b11000100, 0b1011,
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let Inst{19-16} = Rt2;
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let Inst{7-6} = 0b00;
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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}
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let neverHasSideEffects = 1 in
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@ -520,6 +540,10 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010,
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IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{7-6} = 0b00;
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// Some single precision VFP instructions may be executed on both NEON and VFP
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// pipelines.
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let D = VFPNeonDomain;
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}
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// FMRDH: SPR -> GPR
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