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* Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.
This enables the removal of some explicit type casts. * Rename immZExt8 to i16ZExt8 as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24682 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -143,15 +143,21 @@ class XS { bits<4> Prefix = 12; }
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//===----------------------------------------------------------------------===//
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// Pattern fragments...
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//
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def immSExt8 : PatLeaf<(imm), [{
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// immSExt8 predicate - True if the immediate fits in a 8-bit sign extended
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// field.
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def i16SExt8 : PatLeaf<(i16 imm), [{
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// i16SExt8 predicate - True if the 16-bit immediate fits in a 8-bit
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// sign extended field.
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return (int)N->getValue() == (signed char)N->getValue();
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}]>;
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def immZExt8 : PatLeaf<(imm), [{
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// immZExt8 predicate - True if the immediate fits in a 8-bit zero extended
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// field.
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def i32SExt8 : PatLeaf<(i32 imm), [{
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// i32SExt8 predicate - True if the 32-bit immediate fits in a 8-bit
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// sign extended field.
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return (int)N->getValue() == (signed char)N->getValue();
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}]>;
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def i16ZExt8 : PatLeaf<(i16 imm), [{
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// i16ZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero
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// extended field.
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return (unsigned)N->getValue() == (unsigned char)N->getValue();
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}]>;
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@ -348,15 +354,15 @@ def OUT32rr : I<0xEF, RawFrm, (ops),
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def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
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"out{b} {%al, $port|$port, %AL}",
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[(writeport AL, (i16 immZExt8:$port))]>,
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[(writeport AL, (i16 i16ZExt8:$port))]>,
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Imp<[AL], []>;
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def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
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"out{w} {%ax, $port|$port, %AX}",
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[(writeport AX, (i16 immZExt8:$port))]>,
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[(writeport AX, (i16 i16ZExt8:$port))]>,
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Imp<[AX], []>, OpSize;
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def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
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"out{l} {%eax, $port|$port, %EAX}",
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[(writeport EAX, (i16 immZExt8:$port))]>,
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[(writeport EAX, (i16 i16ZExt8:$port))]>,
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Imp<[EAX], []>;
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//===----------------------------------------------------------------------===//
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@ -764,11 +770,11 @@ def AND32ri : Ii32<0x81, MRM4r,
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def AND16ri8 : Ii8<0x83, MRM4r,
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(ops R16:$dst, R16:$src1, i16i8imm:$src2),
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"and{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (and R16:$src1, immSExt8:$src2))]>, OpSize;
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[(set R16:$dst, (and R16:$src1, i16SExt8:$src2))]>, OpSize;
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def AND32ri8 : Ii8<0x83, MRM4r,
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(ops R32:$dst, R32:$src1, i32i8imm:$src2),
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"and{l} {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (and R32:$src1, immSExt8:$src2))]>;
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[(set R32:$dst, (and R32:$src1, i32SExt8:$src2))]>;
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let isTwoAddress = 0 in {
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def AND8mr : I<0x20, MRMDestMem,
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@ -828,10 +834,10 @@ def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
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def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
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"or{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (or R16:$src1, immSExt8:$src2))]>, OpSize;
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[(set R16:$dst, (or R16:$src1, i16SExt8:$src2))]>, OpSize;
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def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
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"or{l} {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (or R32:$src1, immSExt8:$src2))]>;
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[(set R32:$dst, (or R32:$src1, i32SExt8:$src2))]>;
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let isTwoAddress = 0 in {
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def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
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"or{b} {$src, $dst|$dst, $src}", []>;
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@ -892,11 +898,11 @@ def XOR32ri : Ii32<0x81, MRM6r,
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def XOR16ri8 : Ii8<0x83, MRM6r,
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(ops R16:$dst, R16:$src1, i16i8imm:$src2),
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"xor{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (xor R16:$src1, immSExt8:$src2))]>, OpSize;
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[(set R16:$dst, (xor R16:$src1, i16SExt8:$src2))]>, OpSize;
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def XOR32ri8 : Ii8<0x83, MRM6r,
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(ops R32:$dst, R32:$src1, i32i8imm:$src2),
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"xor{l} {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (xor R32:$src1, immSExt8:$src2))]>;
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[(set R32:$dst, (xor R32:$src1, i32SExt8:$src2))]>;
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let isTwoAddress = 0 in {
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def XOR8mr : I<0x30, MRMDestMem,
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(ops i8mem :$dst, R8 :$src),
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@ -1199,10 +1205,10 @@ def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
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// FIXME: move ADD16ri8 above ADD16ri to optimize for space.
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def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
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"add{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (add R16:$src1, immSExt8:$src2))]>, OpSize;
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[(set R16:$dst, (add R16:$src1, i16SExt8:$src2))]>, OpSize;
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def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
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"add{l} {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (add R32:$src1, immSExt8:$src2))]>;
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[(set R32:$dst, (add R32:$src1, i32SExt8:$src2))]>;
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let isTwoAddress = 0 in {
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def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
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@ -1225,10 +1231,10 @@ let isTwoAddress = 0 in {
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[(store (add (load addr:$dst), (i32 imm:$src2)), addr:$dst)]>;
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def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
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"add{w} {$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), (i16 immSExt8:$src2)), addr:$dst)]>, OpSize;
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[(store (add (load addr:$dst), i16SExt8:$src2), addr:$dst)]>, OpSize;
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def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
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"add{l} {$src2, $dst|$dst, $src2}",
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[(store (add (load addr:$dst), (i32 immSExt8:$src2)), addr:$dst)]>;
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[(store (add (load addr:$dst), i32SExt8:$src2), addr:$dst)]>;
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}
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let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
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@ -1281,10 +1287,10 @@ def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
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[(set R32:$dst, (sub R32:$src1, imm:$src2))]>;
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def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
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"sub{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (sub R16:$src1, immSExt8:$src2))]>, OpSize;
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[(set R16:$dst, (sub R16:$src1, i16SExt8:$src2))]>, OpSize;
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def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
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"sub{l} {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (sub R32:$src1, immSExt8:$src2))]>;
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[(set R32:$dst, (sub R32:$src1, i32SExt8:$src2))]>;
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let isTwoAddress = 0 in {
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def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
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"sub{b} {$src2, $dst|$dst, $src2}",
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@ -1306,10 +1312,10 @@ let isTwoAddress = 0 in {
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[(store (sub (load addr:$dst), (i32 imm:$src2)), addr:$dst)]>;
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def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2),
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"sub{w} {$src2, $dst|$dst, $src2}",
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[(store (sub (load addr:$dst), (i16 immSExt8:$src2)), addr:$dst)]>, OpSize;
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[(store (sub (load addr:$dst), i16SExt8:$src2), addr:$dst)]>, OpSize;
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def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2),
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"sub{l} {$src2, $dst|$dst, $src2}",
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[(store (sub (load addr:$dst), (i32 immSExt8:$src2)), addr:$dst)]>;
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[(store (sub (load addr:$dst), i32SExt8:$src2), addr:$dst)]>;
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}
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def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
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@ -1373,11 +1379,11 @@ def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32
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def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8
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(ops R16:$dst, R16:$src1, i16i8imm:$src2),
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"imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set R16:$dst, (mul R16:$src1, immSExt8:$src2))]>, OpSize;
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[(set R16:$dst, (mul R16:$src1, i16SExt8:$src2))]>, OpSize;
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def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8
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(ops R32:$dst, R32:$src1, i32i8imm:$src2),
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"imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set R32:$dst, (mul R32:$src1, immSExt8:$src2))]>;
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[(set R32:$dst, (mul R32:$src1, i32SExt8:$src2))]>;
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def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16
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(ops R16:$dst, i16mem:$src1, i16imm:$src2),
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@ -1391,11 +1397,11 @@ def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32
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def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8
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(ops R16:$dst, i16mem:$src1, i16i8imm :$src2),
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"imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set R16:$dst, (mul (load addr:$src1), immSExt8:$src2))]>, OpSize;
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[(set R16:$dst, (mul (load addr:$src1), i16SExt8:$src2))]>, OpSize;
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def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8
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(ops R32:$dst, i32mem:$src1, i32i8imm: $src2),
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"imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set R32:$dst, (mul (load addr:$src1), immSExt8:$src2))]>;
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[(set R32:$dst, (mul (load addr:$src1), i32SExt8:$src2))]>;
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//===----------------------------------------------------------------------===//
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// Test instructions are just like AND, except they don't generate a result.
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