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Add more vector move low and zero-extend patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58752 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -585,6 +585,15 @@ let AddedComplexity = 15 in {
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(MMX_MOVZDI2PDIrr GR32:$src)>;
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}
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let AddedComplexity = 20 in {
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def : Pat<(v8i8 (X86vzmovl (bc_v8i8 (load_mmx addr:$src)))),
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(MMX_MOVZDI2PDIrm addr:$src)>;
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def : Pat<(v4i16 (X86vzmovl (bc_v4i16 (load_mmx addr:$src)))),
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(MMX_MOVZDI2PDIrm addr:$src)>;
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def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))),
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(MMX_MOVZDI2PDIrm addr:$src)>;
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}
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// Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower
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// 8 or 16-bits matter.
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def : Pat<(bc_v8i8 (v2i32 (scalar_to_vector GR32:$src))),
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15
test/CodeGen/X86/mmx-vzmovl.ll
Normal file
15
test/CodeGen/X86/mmx-vzmovl.ll
Normal file
@ -0,0 +1,15 @@
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; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep movd
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; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep movq
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define void @foo(<1 x i64>* %a, <1 x i64>* %b) nounwind {
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entry:
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%0 = load <1 x i64>* %a, align 8 ; <<1 x i64>> [#uses=1]
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%1 = bitcast <1 x i64> %0 to <2 x i32> ; <<2 x i32>> [#uses=1]
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%2 = and <2 x i32> %1, < i32 -1, i32 0 > ; <<2 x i32>> [#uses=1]
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%3 = bitcast <2 x i32> %2 to <1 x i64> ; <<1 x i64>> [#uses=1]
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store <1 x i64> %3, <1 x i64>* %b, align 8
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br label %bb2
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bb2: ; preds = %entry
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ret void
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}
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