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Also replace uses of SRL if that's also folded during ReduceLoadWidth().

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35286 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-03-23 20:55:21 +00:00
parent 5d787bb93e
commit b37b80ce46
1 changed files with 8 additions and 1 deletions
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7
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -2279,6 +2279,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
unsigned EVTBits = MVT::getSizeInBits(EVT); unsigned EVTBits = MVT::getSizeInBits(EVT);
unsigned ShAmt = 0; unsigned ShAmt = 0;
bool CombineSRL = false;
if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
ShAmt = N01->getValue(); ShAmt = N01->getValue();
@@ -2288,6 +2289,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
return SDOperand(); return SDOperand();
ShAmt /= 8; ShAmt /= 8;
CombineSRL = true;
} }
} }
} }
@@ -2317,6 +2319,11 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
: DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT); LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
AddToWorkList(N); AddToWorkList(N);
if (CombineSRL) {
std::vector<SDNode*> NowDead;
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
CombineTo(N->getOperand(0).Val, Load);
} else
CombineTo(N0.Val, Load, Load.getValue(1)); CombineTo(N0.Val, Load, Load.getValue(1));
if (ShAmt) if (ShAmt)
return DAG.getNode(N->getOpcode(), VT, Load); return DAG.getNode(N->getOpcode(), VT, Load);