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https://github.com/c64scene-ar/llvm-6502.git
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Removing several -Wunused-but-set-variable warnings; NFC intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242028 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -906,25 +906,6 @@ void ARMLoadStoreOpt::FormCandidates(const MemOpQueue &MemOps) {
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unsigned Opcode = FirstMI->getOpcode();
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bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
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unsigned Size = getLSMultipleTransferSize(FirstMI);
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// vldm / vstm limit are 32 for S variants, 16 for D variants.
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unsigned Limit;
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switch (Opcode) {
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default:
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Limit = UINT_MAX;
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break;
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case ARM::VSTRS:
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Limit = 32;
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break;
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case ARM::VSTRD:
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Limit = 16;
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break;
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case ARM::VLDRD:
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Limit = 16;
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break;
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case ARM::VLDRS:
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Limit = 32;
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break;
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}
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unsigned SIndex = 0;
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unsigned EIndex = MemOps.size();
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@ -1634,9 +1615,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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MemOpQueue MemOps;
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unsigned CurrBase = 0;
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unsigned CurrOpc = ~0u;
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unsigned CurrSize = 0;
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ARMCC::CondCodes CurrPred = ARMCC::AL;
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unsigned CurrPredReg = 0;
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unsigned Position = 0;
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assert(Candidates.size() == 0);
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assert(MergeBaseCandidates.size() == 0);
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@ -1652,7 +1631,6 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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if (isMemoryOp(MBBI)) {
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unsigned Opcode = MBBI->getOpcode();
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unsigned Size = getLSMultipleTransferSize(MBBI);
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const MachineOperand &MO = MBBI->getOperand(0);
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unsigned Reg = MO.getReg();
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unsigned Base = getLoadStoreBaseOp(*MBBI).getReg();
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@ -1663,9 +1641,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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// Start of a new chain.
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CurrBase = Base;
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CurrOpc = Opcode;
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CurrSize = Size;
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CurrPred = Pred;
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CurrPredReg = PredReg;
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MemOps.push_back(MemOpQueueEntry(MBBI, Offset, Position));
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continue;
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}
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@ -1737,9 +1713,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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// Reset for the next chain.
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CurrBase = 0;
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CurrOpc = ~0u;
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CurrSize = 0;
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CurrPred = ARMCC::AL;
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CurrPredReg = 0;
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MemOps.clear();
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}
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}
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