diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp
index 74ec06479c4..721c4f26da7 100644
--- a/lib/Target/Mips/MipsSubtarget.cpp
+++ b/lib/Target/Mips/MipsSubtarget.cpp
@@ -85,7 +85,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
       InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
       InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
       AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
-      RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) {
+      RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT), JITInfo() {
   std::string CPUName = CPU;
   CPUName = selectMipsCPU(TT, CPUName);
 
diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index bff656ff125..ef8e27a5e1a 100644
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -14,6 +14,7 @@
 #ifndef MIPSSUBTARGET_H
 #define MIPSSUBTARGET_H
 
+#include "MipsJITInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
@@ -132,6 +133,8 @@ protected:
   MipsTargetMachine *TM;
 
   Triple TargetTriple;
+
+  MipsJITInfo JITInfo;
 public:
   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                              AntiDepBreakMode& Mode,
@@ -248,6 +251,8 @@ public:
   /// specify which component of the system provides it. Hardware, software, and
   /// hybrid implementations are all valid.
   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
+
+  MipsJITInfo *getJITInfo() { return &JITInfo; }
 };
 } // End llvm namespace
 
diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp
index 25234b90233..e6b077ec008 100644
--- a/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/lib/Target/Mips/MipsTargetMachine.cpp
@@ -89,7 +89,7 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
       Subtarget(TT, CPU, FS, isLittle, RM, this),
       DL(computeDataLayout(Subtarget)), InstrInfo(MipsInstrInfo::create(*this)),
       FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
-      TLInfo(MipsTargetLowering::create(*this)), TSInfo(DL), JITInfo() {
+      TLInfo(MipsTargetLowering::create(*this)), TSInfo(DL) {
   initAsmInfo();
 }
 
diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h
index fee8410d316..79e7e1d3c72 100644
--- a/lib/Target/Mips/MipsTargetMachine.h
+++ b/lib/Target/Mips/MipsTargetMachine.h
@@ -17,7 +17,6 @@
 #include "MipsFrameLowering.h"
 #include "MipsISelLowering.h"
 #include "MipsInstrInfo.h"
-#include "MipsJITInfo.h"
 #include "MipsSelectionDAGInfo.h"
 #include "MipsSubtarget.h"
 #include "llvm/CodeGen/Passes.h"
@@ -43,7 +42,6 @@ class MipsTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<const MipsFrameLowering> FrameLoweringSE;
   std::unique_ptr<const MipsTargetLowering> TLInfoSE;
   MipsSelectionDAGInfo TSInfo;
-  MipsJITInfo JITInfo;
 
 public:
   MipsTargetMachine(const Target &T, StringRef TT,
@@ -71,7 +69,9 @@ public:
                : &getSubtargetImpl()->getInstrItineraryData();
   }
 
-  MipsJITInfo *getJITInfo() override { return &JITInfo; }
+  MipsJITInfo *getJITInfo() override {
+    return Subtarget.getJITInfo();
+  }
 
   const MipsRegisterInfo *getRegisterInfo()  const override {
     return &InstrInfo->getRegisterInfo();