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Use an IndexedMap for LiveVariables::VirtRegInfo.
Provide MRI::getNumVirtRegs() and TRI::index2VirtReg() functions to allow iteration over virtual registers without depending on the representation of virtual register numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123098 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -32,8 +32,10 @@
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SparseBitVector.h"
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#include "llvm/ADT/SparseBitVector.h"
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@ -121,10 +123,9 @@ public:
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private:
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private:
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/// VirtRegInfo - This list is a mapping from virtual register number to
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/// VirtRegInfo - This list is a mapping from virtual register number to
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/// variable information. FirstVirtualRegister is subtracted from the virtual
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/// variable information.
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/// register number before indexing into this list.
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///
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///
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std::vector<VarInfo> VirtRegInfo;
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IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo;
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/// PHIJoins - list of virtual registers that are PHI joins. These registers
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/// PHIJoins - list of virtual registers that are PHI joins. These registers
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/// may have multiple definitions, and they require special handling when
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/// may have multiple definitions, and they require special handling when
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@ -216,10 +216,14 @@ public:
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///
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///
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unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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/// getNumVirtRegs - Return the number of virtual registers created.
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///
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unsigned getNumVirtRegs() const { return VRegInfo.size(); }
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/// getLastVirtReg - Return the highest currently assigned virtual register.
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/// getLastVirtReg - Return the highest currently assigned virtual register.
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///
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///
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unsigned getLastVirtReg() const {
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unsigned getLastVirtReg() const {
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return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
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return TargetRegisterInfo::index2VirtReg(getNumVirtRegs() - 1);
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}
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}
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/// getRegClassVirtRegs - Return the list of virtual registers of the given
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/// getRegClassVirtRegs - Return the list of virtual registers of the given
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@ -321,6 +321,12 @@ public:
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return Reg >= FirstVirtualRegister;
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return Reg >= FirstVirtualRegister;
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}
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}
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/// index2VirtReg - Convert a 0-based index to a virtual register number.
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/// This is the inverse operation of VirtReg2IndexFunctor below.
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static unsigned index2VirtReg(unsigned Index) {
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return Index + FirstVirtualRegister;
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}
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/// printReg - Print a virtual or physical register on OS.
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/// printReg - Print a virtual or physical register on OS.
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void printReg(unsigned Reg, raw_ostream &OS) const;
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void printReg(unsigned Reg, raw_ostream &OS) const;
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@ -31,7 +31,6 @@
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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@ -82,13 +81,7 @@ void LiveVariables::VarInfo::dump() const {
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LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
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LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
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assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
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assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
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"getVarInfo: not a virtual register!");
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"getVarInfo: not a virtual register!");
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RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
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VirtRegInfo.grow(RegIdx);
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if (RegIdx >= VirtRegInfo.size()) {
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if (RegIdx >= 2*VirtRegInfo.size())
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VirtRegInfo.resize(RegIdx*2);
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else
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VirtRegInfo.resize(2*VirtRegInfo.size());
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}
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return VirtRegInfo[RegIdx];
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return VirtRegInfo[RegIdx];
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}
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}
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@ -501,9 +494,6 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
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std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
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PHIJoins.clear();
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PHIJoins.clear();
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/// Get some space for a respectable number of registers.
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VirtRegInfo.resize(64);
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analyzePHINodes(mf);
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analyzePHINodes(mf);
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// Calculate live variable information in depth first order on the CFG of the
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// Calculate live variable information in depth first order on the CFG of the
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@ -631,19 +621,14 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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// Convert and transfer the dead / killed information we have gathered into
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// Convert and transfer the dead / killed information we have gathered into
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// VirtRegInfo onto MI's.
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// VirtRegInfo onto MI's.
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for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
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for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
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for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
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const unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (VirtRegInfo[i].Kills[j] ==
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for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
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MRI->getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
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if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
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VirtRegInfo[i]
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VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
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.Kills[j]->addRegisterDead(i +
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TargetRegisterInfo::FirstVirtualRegister,
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TRI);
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else
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else
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VirtRegInfo[i]
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VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
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.Kills[j]->addRegisterKilled(i +
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}
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TargetRegisterInfo::FirstVirtualRegister,
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TRI);
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// Check to make sure there are no unreachable blocks in the MC CFG for the
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// Check to make sure there are no unreachable blocks in the MC CFG for the
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// function. If so, it is due to a bug in the instruction selector or some
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// function. If so, it is due to a bug in the instruction selector or some
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@ -778,8 +763,8 @@ void LiveVariables::addNewBlock(MachineBasicBlock *BB,
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getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
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getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
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// Update info for all live variables
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// Update info for all live variables
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for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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E = MRI->getLastVirtReg()+1; Reg != E; ++Reg) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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VarInfo &VI = getVarInfo(Reg);
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VarInfo &VI = getVarInfo(Reg);
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if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI))
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if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI))
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VI.AliveBlocks.set(NumNew);
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VI.AliveBlocks.set(NumNew);
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