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- Off by one bugs in maximum displacement calculation / testing.
- In thumb mode, a new constpool island BB size should be 4 + 2 to compensate for the potential padding due to alignment requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33753 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -281,8 +281,10 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
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Scale = 2;
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break;
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}
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unsigned MaxDisp = (1 << (Bits-1)) * Scale;
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ImmBranches.push_back(ImmBranch(I, MaxDisp, isCond, UOpc));
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// Record this immediate branch.
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unsigned MaxOffs = (1 << (Bits-1)) * Scale;
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ImmBranches.push_back(ImmBranch(I, MaxOffs, isCond, UOpc));
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}
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if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
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@ -293,9 +295,10 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
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if (I->getOperand(op).isConstantPoolIndex()) {
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// We found one. The addressing mode tells us the max displacement
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// from the PC that this instruction permits.
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unsigned MaxOffs = 0;
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// Basic size info comes from the TSFlags field.
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unsigned Bits = 0;
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unsigned Scale = 1;
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unsigned TSFlags = I->getInstrDescriptor()->TSFlags;
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switch (TSFlags & ARMII::AddrModeMask) {
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default:
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@ -304,34 +307,42 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
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continue;
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assert(0 && "Unknown addressing mode for CP reference!");
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case ARMII::AddrMode1: // AM1: 8 bits << 2
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MaxOffs = 1 << (8+2); // Taking the address of a CP entry.
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Bits = 8;
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Scale = 4; // Taking the address of a CP entry.
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break;
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case ARMII::AddrMode2:
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MaxOffs = 1 << 12; // +-offset_12
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Bits = 12;
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Scale = 2; // +-offset_12
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break;
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case ARMII::AddrMode3:
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MaxOffs = 1 << 8; // +-offset_8
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Bits = 8;
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Scale = 2; // +-offset_8
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break;
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// addrmode4 has no immediate offset.
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case ARMII::AddrMode5:
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MaxOffs = 1 << (8+2); // +-(offset_8*4)
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Bits = 8;
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Scale = 4; // +-(offset_8*4)
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break;
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case ARMII::AddrModeT1:
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MaxOffs = 1 << 5;
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Bits = 5; // +offset_5
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break;
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case ARMII::AddrModeT2:
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MaxOffs = 1 << (5+1);
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Bits = 5;
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Scale = 2; // +(offset_5*2)
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break;
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case ARMII::AddrModeT4:
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MaxOffs = 1 << (5+2);
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Bits = 5;
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Scale = 4; // +(offset_5*4)
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break;
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case ARMII::AddrModeTs:
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MaxOffs = 1 << (8+2);
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Bits = 8;
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Scale = 4; // +(offset_8*4)
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break;
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}
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// Remember that this is a user of a CP entry.
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MachineInstr *CPEMI =CPEMIs[I->getOperand(op).getConstantPoolIndex()];
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unsigned MaxOffs = (1 << (Bits-1)) * Scale;
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CPUsers.push_back(CPUser(I, CPEMI, MaxOffs));
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// Instructions can only use one CP entry, don't bother scanning the
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@ -514,12 +525,12 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &Fn, CPUser &U){
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// TODO: Search for the best place to split the code. In practice, using
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// loop nesting information to insert these guys outside of loops would be
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// sufficient.
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bool isThumb = AFI->isThumbFunction();
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if (&UserMBB->back() == UserMI) {
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assert(BBHasFallthrough(UserMBB) && "Expected a fallthrough BB!");
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NewMBB = next(MachineFunction::iterator(UserMBB));
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// Add an unconditional branch from UserMBB to fallthrough block.
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// Note the new unconditional branch is not being recorded.
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bool isThumb = AFI->isThumbFunction();
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BuildMI(UserMBB, TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewMBB);
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BBSizes[UserMBB->getNumber()] += isThumb ? 2 : 4;
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} else {
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@ -539,11 +550,13 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &Fn, CPUser &U){
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unsigned ID = NextUID++;
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unsigned CPI = CPEMI->getOperand(1).getConstantPoolIndex();
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unsigned Size = CPEMI->getOperand(2).getImm();
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// Build a new CPE for this user.
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U.CPEMI = BuildMI(NewIsland, TII->get(ARM::CONSTPOOL_ENTRY))
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.addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
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// Compensate for .align 2 in thumb mode.
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if (isThumb) Size += 2;
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// Increase the size of the island block to account for the new entry.
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BBSizes[NewIsland->getNumber()] += Size;
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@ -574,7 +587,7 @@ bool ARMConstantIslands::BBIsInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
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<< *MI);
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if (BrOffset <= DestOffset) {
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if (DestOffset - BrOffset < MaxDisp)
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if (DestOffset - BrOffset <= MaxDisp)
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return true;
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} else {
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if (BrOffset - DestOffset <= MaxDisp)
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