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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
Define load instructions with base+immediate offset addressing mode
using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
dd8b1015c8
commit
b434a8130f
@ -909,14 +909,80 @@ def : Pat < (i64 (load ADDRriS11_3:$addr)),
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(LDrid ADDRriS11_3:$addr) >;
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// Load - Base with Immediate offset addressing mode
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multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
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bit isNot, bit isPredNew> {
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let PNewValue = #!if(isPredNew, "new", "") in
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def #NAME# : LDInst2<(outs RC:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
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#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#"$dst = "#mnemonic#"($src2+#$src3)",
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[]>;
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}
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let isPredicable = 1, AddedComplexity = 20 in
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def LDrid_indexed : LDInst<(outs DoubleRegs:$dst),
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(ins IntRegs:$src1, s11_3Imm:$offset),
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"$dst = memd($src1+#$offset)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (load (add (i32 IntRegs:$src1),
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s11_3ImmPred:$offset))))]>;
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multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
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bit PredNot> {
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let PredSense = #!if(PredNot, "false", "true") in {
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defm _c#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
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}
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}
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let isExtendable = 1, neverHasSideEffects = 1 in
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multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
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Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
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bits<5> PredImmBits> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
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let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
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isPredicable = 1, AddedComplexity = 20 in
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def #NAME# : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
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"$dst = "#mnemonic#"($src1+#$offset)",
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[]>;
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let opExtendable = 3, isExtentSigned = 0, opExtentBits = PredImmBits,
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isPredicated = 1 in {
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defm Pt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 0 >;
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defm NotPt : LD_Idxd_Pred<mnemonic, RC, predImmOp, 1 >;
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}
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}
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}
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let addrMode = BaseImmOffset in {
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defm LDrib_indexed: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext,
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11, 6>, AddrModeRel;
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defm LDriub_indexed: LD_Idxd <"memub" , "LDriub", IntRegs, s11_0Ext, u6_0Ext,
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11, 6>, AddrModeRel;
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defm LDrih_indexed: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
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12, 7>, AddrModeRel;
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defm LDriuh_indexed: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
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12, 7>, AddrModeRel;
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defm LDriw_indexed: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
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13, 8>, AddrModeRel;
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defm LDrid_indexed: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
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14, 9>, AddrModeRel;
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}
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let AddedComplexity = 20 in {
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def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
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(LDrib_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
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def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
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(LDriub_indexed IntRegs:$src1, s11_0ExtPred:$offset) >;
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def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
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(LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
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def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
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(LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
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def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
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(LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
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def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
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(LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
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}
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let neverHasSideEffects = 1 in
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def LDrid_GP : LDInst2<(outs DoubleRegs:$dst),
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@ -992,44 +1058,10 @@ let hasCtrlDep = 1, neverHasSideEffects = 1 in {
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PredNewRel;
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}
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// Load doubleword conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_indexed_cPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
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"if ($src1) $dst = memd($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_indexed_cNotPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
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"if (!$src1) $dst = memd($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_indexed_cdnPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
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"if ($src1.new) $dst = memd($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrid_indexed_cdnNotPt : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3),
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"if (!$src1.new) $dst = memd($src2+#$src3)",
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[]>;
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// Load byte any-extend.
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def : Pat < (i32 (extloadi8 ADDRriS11_0:$addr)),
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(i32 (LDrib ADDRriS11_0:$addr)) >;
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// Indexed load byte.
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let isPredicable = 1, AddedComplexity = 20 in
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def LDrib_indexed : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s11_0Imm:$offset),
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"$dst = memb($src1+#$offset)",
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[(set (i32 IntRegs:$dst),
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(i32 (sextloadi8 (add (i32 IntRegs:$src1),
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s11_0ImmPred:$offset))))]>;
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// Indexed load byte any-extend.
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let AddedComplexity = 20 in
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def : Pat < (i32 (extloadi8 (add IntRegs:$src1, s11_0ImmPred:$offset))),
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@ -1056,41 +1088,6 @@ def LDub_GP : LDInst2<(outs IntRegs:$dst),
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[]>,
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Requires<[NoV4T]>;
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// Load byte conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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"if ($src1) $dst = memb($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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"if (!$src1) $dst = memb($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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"if ($src1.new) $dst = memb($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrib_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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"if (!$src1.new) $dst = memb($src2+#$src3)",
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[]>;
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// Load halfword.
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let isPredicable = 1, AddedComplexity = 20 in
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def LDrih_indexed : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s11_1Imm:$offset),
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"$dst = memh($src1+#$offset)",
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[(set (i32 IntRegs:$dst),
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(i32 (sextloadi16 (add (i32 IntRegs:$src1),
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s11_1ImmPred:$offset))))]>;
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def : Pat < (i32 (extloadi16 ADDRriS11_1:$addr)),
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(i32 (LDrih ADDRriS11_1:$addr))>;
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@ -1119,43 +1116,9 @@ def LDuh_GP : LDInst2<(outs IntRegs:$dst),
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[]>,
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Requires<[NoV4T]>;
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// Load halfword conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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"if ($src1) $dst = memh($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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"if (!$src1) $dst = memh($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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"if ($src1.new) $dst = memh($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDrih_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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"if (!$src1.new) $dst = memh($src2+#$src3)",
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[]>;
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// Load unsigned byte.
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def : Pat < (i32 (zextloadi1 ADDRriS11_0:$addr)),
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(i32 (LDriub ADDRriS11_0:$addr))>;
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let isPredicable = 1, AddedComplexity = 20 in
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def LDriub_indexed : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s11_0Imm:$offset),
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"$dst = memub($src1+#$offset)",
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[(set (i32 IntRegs:$dst),
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(i32 (zextloadi8 (add (i32 IntRegs:$src1),
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s11_0ImmPred:$offset))))]>;
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let AddedComplexity = 20 in
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def : Pat < (i32 (zextloadi1 (add IntRegs:$src1, s11_0ImmPred:$offset))),
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(i32 (LDriub_indexed IntRegs:$src1, s11_0ImmPred:$offset))>;
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@ -1167,41 +1130,7 @@ def LDriub_GP : LDInst2<(outs IntRegs:$dst),
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[]>,
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Requires<[NoV4T]>;
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// Load unsigned byte conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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"if ($src1) $dst = memub($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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"if (!$src1) $dst = memub($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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"if ($src1.new) $dst = memub($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriub_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3),
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"if (!$src1.new) $dst = memub($src2+#$src3)",
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[]>;
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// Load unsigned halfword.
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// Indexed load unsigned halfword.
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let isPredicable = 1, AddedComplexity = 20 in
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def LDriuh_indexed : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s11_1Imm:$offset),
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"$dst = memuh($src1+#$offset)",
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[(set (i32 IntRegs:$dst),
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(i32 (zextloadi16 (add (i32 IntRegs:$src1),
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s11_1ImmPred:$offset))))]>;
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let neverHasSideEffects = 1 in
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def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
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(ins globaladdress:$global, u16Imm:$offset),
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@ -1209,33 +1138,6 @@ def LDriuh_GP : LDInst2<(outs IntRegs:$dst),
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[]>,
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Requires<[NoV4T]>;
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// Load unsigned halfword conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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"if ($src1) $dst = memuh($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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"if (!$src1) $dst = memuh($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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"if ($src1.new) $dst = memuh($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriuh_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3),
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"if (!$src1.new) $dst = memuh($src2+#$src3)",
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[]>;
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// Load word.
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// Load predicate.
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let Defs = [R10,R11,D5], neverHasSideEffects = 1 in
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def LDriw_pred : LDInst<(outs PredRegs:$dst),
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@ -1244,13 +1146,6 @@ def LDriw_pred : LDInst<(outs PredRegs:$dst),
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[]>;
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// Indexed load.
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let isPredicable = 1, AddedComplexity = 20 in
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def LDriw_indexed : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s11_2Imm:$offset),
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"$dst = memw($src1+#$offset)",
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[(set IntRegs:$dst, (i32 (load (add IntRegs:$src1,
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s11_2ImmPred:$offset))))]>;
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let neverHasSideEffects = 1 in
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def LDriw_GP : LDInst2<(outs IntRegs:$dst),
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(ins globaladdress:$global, u16Imm:$offset),
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@ -1265,31 +1160,6 @@ def LDw_GP : LDInst2<(outs IntRegs:$dst),
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[]>,
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Requires<[NoV4T]>;
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// Load word conditionally.
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_indexed_cPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
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"if ($src1) $dst = memw($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_indexed_cNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
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"if (!$src1) $dst = memw($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_indexed_cdnPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
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"if ($src1.new) $dst = memw($src2+#$src3)",
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[]>;
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let neverHasSideEffects = 1, isPredicated = 1 in
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def LDriw_indexed_cdnNotPt : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3),
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"if (!$src1.new) $dst = memw($src2+#$src3)",
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[]>;
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// Deallocate stack frame.
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let Defs = [R29, R30, R31], Uses = [R29], neverHasSideEffects = 1 in {
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def DEALLOCFRAME : LDInst2<(outs), (ins i32imm:$amt1),
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