6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-13 22:26:11 +00:00
Code Issues Projects Releases Wiki Activity

Whitespace and formatting.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83285 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2009-10-04 18:18:39 +00:00
parent 52020782ad
commit b44fad7f95
1 changed files with 16 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
lib/CodeGen/MachineVerifier.cpp
View File

@ -238,9 +238,7 @@ void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
<< "- function: " << MF->getFunction()->getNameStr() << "\n"; << "- function: " << MF->getFunction()->getNameStr() << "\n";
} }
void void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
{
assert(MBB); assert(MBB);
report(msg, MBB->getParent()); report(msg, MBB->getParent());
*OS << "- basic block: " << MBB->getBasicBlock()->getNameStr() *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
@ -248,19 +246,15 @@ MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
<< " (#" << MBB->getNumber() << ")\n"; << " (#" << MBB->getNumber() << ")\n";
} }
void void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
MachineVerifier::report(const char *msg, const MachineInstr *MI)
{
assert(MI); assert(MI);
report(msg, MI->getParent()); report(msg, MI->getParent());
*OS << "- instruction: "; *OS << "- instruction: ";
MI->print(*OS, TM); MI->print(*OS, TM);
} }
void void MachineVerifier::report(const char *msg,
MachineVerifier::report(const char *msg, const MachineOperand *MO, unsigned MONum) {
const MachineOperand *MO, unsigned MONum)
{
assert(MO); assert(MO);
report(msg, MO->getParent()); report(msg, MO->getParent());
*OS << "- operand " << MONum << ": "; *OS << "- operand " << MONum << ": ";
@ -268,9 +262,7 @@ MachineVerifier::report(const char *msg,
*OS << "\n"; *OS << "\n";
} }
void void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
MachineVerifier::markReachable(const MachineBasicBlock *MBB)
{
BBInfo &MInfo = MBBInfoMap[MBB]; BBInfo &MInfo = MBBInfoMap[MBB];
if (!MInfo.reachable) { if (!MInfo.reachable) {
MInfo.reachable = true; MInfo.reachable = true;
@ -280,9 +272,7 @@ MachineVerifier::markReachable(const MachineBasicBlock *MBB)
} }
} }
void void MachineVerifier::visitMachineFunctionBefore() {
MachineVerifier::visitMachineFunctionBefore()
{
regsReserved = TRI->getReservedRegs(*MF); regsReserved = TRI->getReservedRegs(*MF);
// A sub-register of a reserved register is also reserved // A sub-register of a reserved register is also reserved
@ -297,9 +287,7 @@ MachineVerifier::visitMachineFunctionBefore()
markReachable(&MF->front()); markReachable(&MF->front());
} }
void void MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
{
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
// Start with minimal CFG sanity checks. // Start with minimal CFG sanity checks.
@ -462,9 +450,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
regsDefined.clear(); regsDefined.clear();
} }
void void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
{
const TargetInstrDesc &TI = MI->getDesc(); const TargetInstrDesc &TI = MI->getDesc();
if (MI->getNumOperands() < TI.getNumOperands()) { if (MI->getNumOperands() < TI.getNumOperands()) {
report("Too few operands", MI); report("Too few operands", MI);
@ -474,8 +460,7 @@ MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
} }
void void
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
{
const MachineInstr *MI = MO->getParent(); const MachineInstr *MI = MO->getParent();
const TargetInstrDesc &TI = MI->getDesc(); const TargetInstrDesc &TI = MI->getDesc();
@ -608,9 +593,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
} }
} }
void void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
{
BBInfo &MInfo = MBBInfoMap[MI->getParent()]; BBInfo &MInfo = MBBInfoMap[MI->getParent()];
set_union(MInfo.regsKilled, regsKilled); set_union(MInfo.regsKilled, regsKilled);
set_subtract(regsLive, regsKilled); set_subtract(regsLive, regsKilled);
@ -650,8 +633,7 @@ MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
} }
void void
MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
{
MBBInfoMap[MBB].regsLiveOut = regsLive; MBBInfoMap[MBB].regsLiveOut = regsLive;
regsLive.clear(); regsLive.clear();
} }
@ -659,9 +641,7 @@ MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
// Calculate the largest possible vregsPassed sets. These are the registers that // Calculate the largest possible vregsPassed sets. These are the registers that
// can pass through an MBB live, but may not be live every time. It is assumed // can pass through an MBB live, but may not be live every time. It is assumed
// that all vregsPassed sets are empty before the call. // that all vregsPassed sets are empty before the call.
void void MachineVerifier::calcMaxRegsPassed() {
MachineVerifier::calcMaxRegsPassed()
{
// First push live-out regs to successors' vregsPassed. Remember the MBBs that // First push live-out regs to successors' vregsPassed. Remember the MBBs that
// have any vregsPassed. // have any vregsPassed.
DenseSet<const MachineBasicBlock*> todo; DenseSet<const MachineBasicBlock*> todo;
@ -699,9 +679,7 @@ MachineVerifier::calcMaxRegsPassed()
// Calculate the minimum vregsPassed set. These are the registers that always // Calculate the minimum vregsPassed set. These are the registers that always
// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
// been called earlier. // been called earlier.
void void MachineVerifier::calcMinRegsPassed() {
MachineVerifier::calcMinRegsPassed()
{
DenseSet<const MachineBasicBlock*> todo; DenseSet<const MachineBasicBlock*> todo;
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
MFI != MFE; ++MFI) MFI != MFE; ++MFI)
@ -736,9 +714,7 @@ MachineVerifier::calcMinRegsPassed()
// Check PHI instructions at the beginning of MBB. It is assumed that // Check PHI instructions at the beginning of MBB. It is assumed that
// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid. // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
void void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
{
for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end(); for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) { BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
DenseSet<const MachineBasicBlock*> seen; DenseSet<const MachineBasicBlock*> seen;
@ -767,9 +743,7 @@ MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
} }
} }
void void MachineVerifier::visitMachineFunctionAfter() {
MachineVerifier::visitMachineFunctionAfter()
{
calcMaxRegsPassed(); calcMaxRegsPassed();
// With the maximal set of vregsPassed we can verify dead-in registers. // With the maximal set of vregsPassed we can verify dead-in registers.