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Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15952 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -33,6 +33,7 @@ using namespace llvm;
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namespace {
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Statistic<> GEPFolds("ppc-codegen", "Number of GEPs folded");
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Statistic<> NumSetCC("ppc-codegen", "Number of SetCC straight-lined");
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/// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
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/// PPC Representation.
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@ -280,6 +281,10 @@ namespace {
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abort();
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}
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unsigned ExtendOrClear(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned Reg, const Type *CompTy);
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/// promote32 - Make a value 32-bits wide, and put it somewhere.
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///
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void promote32(unsigned targetReg, const ValueRecord &VR);
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@ -959,6 +964,33 @@ void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
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}
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unsigned ISel::ExtendOrClear(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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unsigned Reg, const Type *CompTy) {
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unsigned Class = getClassB(CompTy);
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// Before we do a comparison or SetCC, we have to make sure that we truncate
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// the source registers appropriately.
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if (Class == cByte) {
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unsigned TmpReg = makeAnotherReg(CompTy);
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if (CompTy->isSigned())
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BuildMI(*MBB, IP, PPC::EXTSB, 1, TmpReg).addReg(Reg);
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else
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BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Reg).addImm(0)
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.addImm(24).addImm(31);
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Reg = TmpReg;
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} else if (Class == cShort) {
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unsigned TmpReg = makeAnotherReg(CompTy);
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if (CompTy->isSigned())
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BuildMI(*MBB, IP, PPC::EXTSH, 1, TmpReg).addReg(Reg);
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else
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BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Reg).addImm(0)
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.addImm(16).addImm(31);
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Reg = TmpReg;
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}
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return Reg;
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}
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/// EmitComparison - emits a comparison of the two operands, returning the
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/// extended setcc code to use. The result is in CR0.
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///
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@ -968,27 +1000,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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// The arguments are already supposed to be of the same type.
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const Type *CompTy = Op0->getType();
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unsigned Class = getClassB(CompTy);
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unsigned Op0r = getReg(Op0, MBB, IP);
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// Before we do a comparison, we have to make sure that we're truncating our
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// registers appropriately.
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if (Class == cByte) {
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unsigned TmpReg = makeAnotherReg(CompTy);
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if (CompTy->isSigned())
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BuildMI(*MBB, IP, PPC::EXTSB, 1, TmpReg).addReg(Op0r);
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else
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BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
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.addImm(24).addImm(31);
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Op0r = TmpReg;
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} else if (Class == cShort) {
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unsigned TmpReg = makeAnotherReg(CompTy);
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if (CompTy->isSigned())
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BuildMI(*MBB, IP, PPC::EXTSH, 1, TmpReg).addReg(Op0r);
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else
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BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
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.addImm(16).addImm(31);
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Op0r = TmpReg;
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}
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unsigned Op0r = ExtendOrClear(MBB, IP, getReg(Op0, MBB, IP), CompTy);
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// Use crand for lt, gt and crandc for le, ge
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unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
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@ -1098,13 +1110,148 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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if (canFoldSetCCIntoBranchOrSelect(&I))
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return;
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Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
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const Type *Ty = Op0->getType();
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unsigned Class = getClassB(Ty);
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unsigned Opcode = I.getOpcode();
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unsigned DestReg = getReg(I);
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unsigned OpNum = I.getOpcode();
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const Type *Ty = I.getOperand (0)->getType();
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EmitComparison(OpNum, I.getOperand(0), I.getOperand(1), BB, BB->end());
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// If the comparison type is byte, short, or int, then we can emit a
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// branchless version of the SetCC that puts 0 (false) or 1 (true) in the
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// destination register.
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if (Class <= cInt) {
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++NumSetCC;
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MachineBasicBlock::iterator MI = BB->end();
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unsigned OpNum = getSetCCNumber(Opcode);
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unsigned Op0Reg = getReg(Op0, BB, MI);
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Op0Reg = ExtendOrClear(BB, MI, Op0Reg, Ty);
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unsigned Opcode = getPPCOpcodeForSetCCNumber(OpNum);
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// comparisons against constant zero often have shorter sequences than the
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// general case, handled below.
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ConstantInt *CI = dyn_cast<ConstantInt>(Op1);
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if (CI && CI->getRawValue() == 0) {
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switch(OpNum) {
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case 0: { // eq0
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unsigned TempReg = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::CNTLZW, 1, TempReg).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(TempReg).addImm(5);
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break;
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}
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case 1: { // ne0
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unsigned TempReg = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::ADDIC, 2, TempReg).addReg(Op0Reg).addSImm(-1);
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BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(TempReg).addReg(Op0Reg);
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break;
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}
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case 2: { // lt0, always false if unsigned
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if (Ty->isSigned())
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Op0Reg).addImm(31);
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else
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BuildMI(*BB, MI, PPC::LI, 1, DestReg).addSImm(0);
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break;
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}
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case 3: { // ge0, always true if unsigned
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if (Ty->isSigned()) {
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unsigned TempReg = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::SRWI, 2, TempReg).addReg(Op0Reg).addImm(31);
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BuildMI(*BB, MI, PPC::XORI, 2, DestReg).addReg(TempReg).addImm(1);
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} else {
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BuildMI(*BB, MI, PPC::LI, 1, DestReg).addSImm(1);
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}
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break;
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}
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case 4: { // gt0, equivalent to ne0 if unsigned
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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if (Ty->isSigned()) {
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BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::ANDC, 2, Temp2).addReg(Temp1).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Temp2).addImm(31);
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} else {
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BuildMI(*BB, MI, PPC::ADDIC, 2, Temp1).addReg(Op0Reg).addSImm(-1);
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BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(Temp1).addReg(Op0Reg);
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}
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break;
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}
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case 5: { // le0, equivalent to eq0 if unsigned
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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if (Ty->isSigned()) {
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BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::ORC, 2, Temp2).addReg(Op0Reg).addReg(Temp1);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Temp2).addImm(31);
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} else {
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BuildMI(*BB, MI, PPC::CNTLZW, 1, Temp1).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Temp1).addImm(5);
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}
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break;
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}
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} // switch
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return;
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}
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unsigned Op1Reg = getReg(Op1, BB, MI);
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switch(OpNum) {
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case 0: { // eq
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::SUBF, 2, Temp1).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, MI, PPC::CNTLZW, 1, Temp2).addReg(Temp1);
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BuildMI(*BB, MI, PPC::SRWI, 2, DestReg).addReg(Temp2).addImm(5);
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break;
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}
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case 1: { // ne
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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BuildMI(*BB, MI, PPC::SUBF, 2, Temp1).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, MI, PPC::ADDIC, 2, Temp2).addReg(Temp1).addSImm(-1);
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BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(Temp2).addReg(Temp1);
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break;
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}
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case 2:
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case 4: { // lt, gt
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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unsigned Temp3 = makeAnotherReg(Type::IntTy);
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unsigned Temp4 = makeAnotherReg(Type::IntTy);
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if (OpNum == 4) std::swap(Op0Reg, Op1Reg);
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if (Ty->isSigned()) {
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BuildMI(*BB, MI, PPC::SUBFC, 2, Temp1).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::EQV, 2, Temp2).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SRWI, 2, Temp3).addReg(Temp2).addImm(31);
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BuildMI(*BB, MI, PPC::ADDZE, 1, Temp4).addReg(Temp3);
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BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp4).addImm(0)
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.addImm(31).addImm(31);
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} else {
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BuildMI(*BB, MI, PPC::SUBFC, 2, Temp1).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(*BB, MI, PPC::SUBFE, 2, Temp2).addReg(Temp1).addReg(Temp1);
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BuildMI(*BB, MI, PPC::NEG, 2, DestReg).addReg(Temp2);
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}
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break;
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}
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case 3:
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case 5: { // le, ge
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unsigned Temp1 = makeAnotherReg(Type::IntTy);
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unsigned Temp2 = makeAnotherReg(Type::IntTy);
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unsigned Temp3 = makeAnotherReg(Type::IntTy);
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if (OpNum == 3) std::swap(Op0Reg, Op1Reg);
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if (Ty->isSigned()) {
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BuildMI(*BB, MI, PPC::SRWI, 2, Temp1).addReg(Op0Reg).addImm(31);
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BuildMI(*BB, MI, PPC::SRAWI, 2, Temp2).addReg(Op1Reg).addImm(31);
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BuildMI(*BB, MI, PPC::SUBFC, 2, Temp3).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, MI, PPC::ADDE, 2, DestReg).addReg(Temp2).addReg(Temp1);
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} else {
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BuildMI(*BB, MI, PPC::LI, 1, Temp2).addSImm(-1);
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BuildMI(*BB, MI, PPC::SUBFC, 2, Temp1).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(*BB, MI, PPC::SUBFZE, 1, DestReg).addReg(Temp2);
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}
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break;
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}
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} // switch
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return;
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}
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EmitComparison(Opcode, Op0, Op1, BB, BB->end());
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unsigned PPCOpcode = getPPCOpcodeForSetCCNumber(Opcode);
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MachineBasicBlock *thisMBB = BB;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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@ -1121,7 +1268,7 @@ void ISel::visitSetCondInst(SetCondInst &I) {
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// bCC. But MBB->getFirstTerminator() can't understand this.
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MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().insert(It, copy1MBB);
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BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
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BuildMI(BB, PPCOpcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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F->getBasicBlockList().insert(It, copy0MBB);
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BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
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@ -96,12 +96,14 @@ def CMPLDI : DForm_6_ext<10, 1, 0,
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def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
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def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
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def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
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def CNTLZW : XForm_11<"cntlzw", 31, 26, 0, 0, 0>;
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def CRAND : XLForm_1<"crand", 19, 257, 0, 0>;
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def CRANDC : XLForm_1<"crandc", 19, 129, 0, 0>;
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def CRNOR : XLForm_1<"crnor", 19, 33, 0, 0>;
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def CROR : XLForm_1<"cror", 19, 449, 0, 0>;
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def DIVW : XOForm_1<"divw", 31, 491, 0, 0, 0, 0>;
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def DIVWU : XOForm_1<"divwu", 31, 459, 0, 0, 0, 0>;
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def EQV : XForm_6<"eqv", 31, 284, 0, 0, 0>;
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def EXTSB : XForm_11<"extsb", 31, 954, 0, 0, 0>;
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def EXTSH : XForm_11<"extsh", 31, 922, 0, 0, 0>;
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def FADD : AForm_2<"fadd", 63, 21, 0, 0, 0>;
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@ -150,6 +152,7 @@ def NAND : XForm_6<"nand", 31, 476, 0, 0, 0>;
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def NEG : XOForm_3<"neg", 31, 104, 0, 0, 0, 0>;
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def NOR : XForm_6<"nor", 31, 124, 0, 0, 0>;
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def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">;
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def ORC : XForm_6<"orc", 31, 412, 0, 0, 0>;
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def ORI : DForm_4<24, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2">;
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@ -171,6 +174,7 @@ def SRADI : XSForm_1<"sradi", 31, 413, 0, 1, 0>;
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def SRAWI : XForm_10<"srawi", 31, 824, 0, 0, 0>;
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def SRAD : XForm_6<"srad", 31, 794, 0, 1, 0>;
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def SRAW : XForm_6<"sraw", 31, 792, 0, 0, 0>;
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def SRWI : MForm_2<"srwi", 21, 0, 0, 0>;
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def STB : DForm_3<"stb", 38, 0, 0>;
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def STBU : DForm_3<"stbu", 39, 0, 0>;
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def STBX : XForm_8<"stbx", 31, 215, 0, 0>;
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