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Re-apply r175688, with the changes suggested by Jakob in PR15320.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175809 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lang Hames
2013-02-21 22:16:43 +00:00
parent 5e5529c74c
commit b489e29976
1 changed files with 15 additions and 24 deletions
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39
lib/CodeGen/ExpandPostRAPseudos.cpp
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@ -49,8 +49,6 @@ private:
bool LowerSubregToReg(MachineInstr *MI); bool LowerSubregToReg(MachineInstr *MI);
bool LowerCopy(MachineInstr *MI); bool LowerCopy(MachineInstr *MI);
void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
const TargetRegisterInfo *TRI);
void TransferImplicitDefs(MachineInstr *MI); void TransferImplicitDefs(MachineInstr *MI);
}; };
} // end anonymous namespace } // end anonymous namespace
@ -61,21 +59,6 @@ char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID;
INITIALIZE_PASS(ExpandPostRA, "postrapseudos", INITIALIZE_PASS(ExpandPostRA, "postrapseudos",
"Post-RA pseudo instruction expansion pass", false, false) "Post-RA pseudo instruction expansion pass", false, false)
/// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
/// and the lowered replacement instructions immediately precede it.
/// Mark the replacement instructions with the dead flag.
void
ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
const TargetRegisterInfo *TRI) {
for (MachineBasicBlock::iterator MII =
prior(MachineBasicBlock::iterator(MI)); ; --MII) {
if (MII->addRegisterDead(DstReg, TRI))
break;
assert(MII != MI->getParent()->begin() &&
"copyPhysReg output doesn't reference destination register!");
}
}
/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
/// replacement instructions immediately precede it. Copy any implicit-def /// replacement instructions immediately precede it. Copy any implicit-def
/// operands from MI to the replacement instruction. /// operands from MI to the replacement instruction.
@ -114,6 +97,12 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
if (MI->allDefsAreDead()) {
MI->setDesc(TII->get(TargetOpcode::KILL));
DEBUG(dbgs() << "subreg: replaced by: " << *MI);
return true;
}
if (DstSubReg == InsReg) { if (DstSubReg == InsReg) {
// No need to insert an identify copy instruction. // No need to insert an identify copy instruction.
// Watch out for case like this: // Watch out for case like this:
@ -135,10 +124,6 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
MachineBasicBlock::iterator CopyMI = MI; MachineBasicBlock::iterator CopyMI = MI;
--CopyMI; --CopyMI;
CopyMI->addRegisterDefined(DstReg); CopyMI->addRegisterDefined(DstReg);
// Transfer the kill/dead flags, if needed.
if (MI->getOperand(0).isDead())
TransferDeadFlag(MI, DstSubReg, TRI);
DEBUG(dbgs() << "subreg: " << *CopyMI); DEBUG(dbgs() << "subreg: " << *CopyMI);
} }
@ -148,6 +133,14 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
} }
bool ExpandPostRA::LowerCopy(MachineInstr *MI) { bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
if (MI->allDefsAreDead()) {
DEBUG(dbgs() << "dead copy: " << *MI);
MI->setDesc(TII->get(TargetOpcode::KILL));
DEBUG(dbgs() << "replaced by: " << *MI);
return true;
}
MachineOperand &DstMO = MI->getOperand(0); MachineOperand &DstMO = MI->getOperand(0);
MachineOperand &SrcMO = MI->getOperand(1); MachineOperand &SrcMO = MI->getOperand(1);
@ -155,7 +148,7 @@ bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
DEBUG(dbgs() << "identity copy: " << *MI); DEBUG(dbgs() << "identity copy: " << *MI);
// No need to insert an identity copy instruction, but replace with a KILL // No need to insert an identity copy instruction, but replace with a KILL
// if liveness is changed. // if liveness is changed.
if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) { if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
// We must make sure the super-register gets killed. Replace the // We must make sure the super-register gets killed. Replace the
// instruction with KILL. // instruction with KILL.
MI->setDesc(TII->get(TargetOpcode::KILL)); MI->setDesc(TII->get(TargetOpcode::KILL));
@ -171,8 +164,6 @@ bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
if (DstMO.isDead())
TransferDeadFlag(MI, DstMO.getReg(), TRI);
if (MI->getNumOperands() > 2) if (MI->getNumOperands() > 2)
TransferImplicitDefs(MI); TransferImplicitDefs(MI);
DEBUG({ DEBUG({