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Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86324 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -183,6 +183,13 @@ public:
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void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn);
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/// CheckReturn - Analyze the return values of a function, returning
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/// true if the return can be performed without sret-demotion, and
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/// false otherwise.
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bool CheckReturn(const SmallVectorImpl<EVT> &OutTys,
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const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
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CCAssignFn Fn);
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/// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
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/// incorporating info about the passed values into this state.
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void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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@ -1167,6 +1167,18 @@ public:
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return SDValue(); // this is here to silence compiler errors
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}
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/// CanLowerReturn - This hook should be implemented to check whether the
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/// return values described by the Outs array can fit into the return
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/// registers. If false is returned, an sret-demotion is performed.
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///
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virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<EVT> &OutTys,
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const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
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SelectionDAG &DAG)
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{
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// Return true by default to get preexisting behavior.
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return true;
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}
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/// LowerReturn - This hook must be implemented to lower outgoing
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/// return values, described by the Outs array, into the specified
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/// DAG. The implementation should return the resulting token chain
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@ -77,6 +77,21 @@ CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
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}
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}
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/// CheckReturn - Analyze the return values of a function, returning true if
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/// the return can be performed without sret-demotion, and false otherwise.
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bool CCState::CheckReturn(const SmallVectorImpl<EVT> &OutTys,
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const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
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CCAssignFn Fn) {
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// Determine which register each value should be copied into.
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for (unsigned i = 0, e = OutTys.size(); i != e; ++i) {
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EVT VT = OutTys[i];
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ISD::ArgFlagsTy ArgFlags = ArgsFlags[i];
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if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
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return false;
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}
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return true;
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}
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/// AnalyzeReturn - Analyze the returned values of a return,
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/// incorporating info about the result values into this state.
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void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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@ -947,6 +947,58 @@ SDValue SelectionDAGLowering::getValue(const Value *V) {
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return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
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}
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/// Get the EVTs and ArgFlags collections that represent the return type
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/// of the given function. This does not require a DAG or a return value, and
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/// is suitable for use before any DAGs for the function are constructed.
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static void getReturnInfo(const Function* F, SmallVectorImpl<EVT> &OutVTs,
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SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
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TargetLowering &TLI) {
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const Type* ReturnType = F->getReturnType();
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(TLI, ReturnType, ValueVTs);
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unsigned NumValues = ValueVTs.size();
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if ( NumValues == 0 ) return;
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for (unsigned j = 0, f = NumValues; j != f; ++j) {
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EVT VT = ValueVTs[j];
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
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if (F->paramHasAttr(0, Attribute::SExt))
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ExtendKind = ISD::SIGN_EXTEND;
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else if (F->paramHasAttr(0, Attribute::ZExt))
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ExtendKind = ISD::ZERO_EXTEND;
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// FIXME: C calling convention requires the return type to be promoted to
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// at least 32-bit. But this is not necessary for non-C calling
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// conventions. The frontend should mark functions whose return values
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// require promoting with signext or zeroext attributes.
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if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
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EVT MinVT = TLI.getRegisterType(F->getContext(), MVT::i32);
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if (VT.bitsLT(MinVT))
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VT = MinVT;
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}
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unsigned NumParts = TLI.getNumRegisters(F->getContext(), VT);
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EVT PartVT = TLI.getRegisterType(F->getContext(), VT);
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// 'inreg' on function refers to return value
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ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
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if (F->paramHasAttr(0, Attribute::InReg))
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Flags.setInReg();
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// Propagate extension type if any
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if (F->paramHasAttr(0, Attribute::SExt))
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Flags.setSExt();
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else if (F->paramHasAttr(0, Attribute::ZExt))
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Flags.setZExt();
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for (unsigned i = 0; i < NumParts; ++i)
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{
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OutVTs.push_back(PartVT);
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OutFlags.push_back(Flags);
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}
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}
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}
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void SelectionDAGLowering::visitRet(ReturnInst &I) {
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SDValue Chain = getControlRoot();
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@ -5758,6 +5810,14 @@ void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
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DebugLoc dl = SDL->getCurDebugLoc();
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const TargetData *TD = TLI.getTargetData();
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// Check whether the function can return without sret-demotion.
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SmallVector<EVT, 4> OutVTs;
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SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
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getReturnInfo(&F, OutVTs, OutsFlags, TLI);
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// For now, assert and bail out if it can't.
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assert(TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(), OutVTs, OutsFlags,
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DAG) && "Cannot fit return value in registers!");
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// Set up the incoming argument description vector.
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SmallVector<ISD::InputArg, 16> Ins;
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unsigned Idx = 1;
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@ -1087,6 +1087,17 @@ unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
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#include "X86GenCallingConv.inc"
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bool
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X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<EVT> &OutTys,
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const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
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SelectionDAG &DAG) {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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RVLocs, *DAG.getContext());
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return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
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}
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SDValue
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X86TargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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@ -699,6 +699,12 @@ namespace llvm {
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG);
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virtual bool
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CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<EVT> &OutTys,
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const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
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SelectionDAG &DAG);
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void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG, unsigned NewOp);
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