6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-24 22:24:54 +00:00
Code Issues Projects Releases Wiki Activity

Provide AltOrders for specifying alternative allocation orders.

Browse Source 
A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.

This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-06-18 00:50:49 +00:00
parent edb15d6872
commit b4c704877d
4 changed files with 75 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
utils/TableGen/CodeGenRegisters.cpp
View File

@@ -172,10 +172,28 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
}
assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
// Default allocation order always contains all registers.
Elements = RegBank.getSets().expand(R);
for (unsigned i = 0, e = Elements->size(); i != e; ++i)
Members.insert(RegBank.getReg((*Elements)[i]));
// Alternative allocation orders may be subsets.
ListInit *Alts = R->getValueAsListInit("AltOrders");
AltOrders.resize(Alts->size());
SetTheory::RecSet Order;
for (unsigned i = 0, e = Alts->size(); i != e; ++i) {
RegBank.getSets().evaluate(Alts->getElement(i), Order);
AltOrders[i].append(Order.begin(), Order.end());
// Verify that all altorder members are regclass members.
while (!Order.empty()) {
CodeGenRegister *Reg = RegBank.getReg(Order.back());
Order.pop_back();
if (!contains(Reg))
throw TGError(R->getLoc(), " AltOrder register " + Reg->getName() +
" is not a class member");
}
}
// SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
ListInit *SRC = R->getValueAsListInit("SubRegClasses");
for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
@@ -209,6 +227,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
Allocatable = R->getValueAsBit("isAllocatable");
MethodBodies = R->getValueAsCode("MethodBodies");
MethodProtos = R->getValueAsCode("MethodProtos");
AltOrderSelect = R->getValueAsCode("AltOrderSelect");
}
bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {