mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-23 01:24:30 +00:00
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
This was done with the following sed invocation to catch label lines demarking function boundaries:
sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stephen Lin
@ -1,7 +1,7 @@
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|||||||
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
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define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
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; CHECK: test_simple:
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; CHECK-LABEL: test_simple:
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%valadd = add i128 %a, %b
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%valadd = add i128 %a, %b
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; CHECK: adds [[ADDLO:x[0-9]+]], x0, x2
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; CHECK: adds [[ADDLO:x[0-9]+]], x0, x2
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@ -16,7 +16,7 @@ define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
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}
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}
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|
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define i128 @test_imm(i128 %a) {
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define i128 @test_imm(i128 %a) {
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; CHECK: test_imm:
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; CHECK-LABEL: test_imm:
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%val = add i128 %a, 12
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%val = add i128 %a, 12
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; CHECK: adds x0, x0, #12
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; CHECK: adds x0, x0, #12
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@ -27,7 +27,7 @@ define i128 @test_imm(i128 %a) {
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}
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}
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define i128 @test_shifted(i128 %a, i128 %b) {
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define i128 @test_shifted(i128 %a, i128 %b) {
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; CHECK: test_shifted:
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; CHECK-LABEL: test_shifted:
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%rhs = shl i128 %b, 45
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%rhs = shl i128 %b, 45
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@ -40,7 +40,7 @@ define i128 @test_shifted(i128 %a, i128 %b) {
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}
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}
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|
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define i128 @test_extended(i128 %a, i16 %b) {
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define i128 @test_extended(i128 %a, i16 %b) {
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; CHECK: test_extended:
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; CHECK-LABEL: test_extended:
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%ext = sext i16 %b to i128
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%ext = sext i16 %b to i128
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%rhs = shl i128 %ext, 3
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%rhs = shl i128 %ext, 3
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@ -4,7 +4,7 @@
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@var64 = global i64 0
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@var64 = global i64 0
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define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_lsl_arith:
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; CHECK-LABEL: test_lsl_arith:
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%rhs1 = load volatile i32* @var32
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%rhs1 = load volatile i32* @var32
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%shift1 = shl i32 %rhs1, 18
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%shift1 = shl i32 %rhs1, 18
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@ -73,7 +73,7 @@ define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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}
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}
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define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_lsr_arith:
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; CHECK-LABEL: test_lsr_arith:
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%shift1 = lshr i32 %rhs32, 18
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%shift1 = lshr i32 %rhs32, 18
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%val1 = add i32 %lhs32, %shift1
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%val1 = add i32 %lhs32, %shift1
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@ -132,7 +132,7 @@ define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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}
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}
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define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_asr_arith:
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; CHECK-LABEL: test_asr_arith:
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|
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%shift1 = ashr i32 %rhs32, 18
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%shift1 = ashr i32 %rhs32, 18
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%val1 = add i32 %lhs32, %shift1
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%val1 = add i32 %lhs32, %shift1
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@ -191,7 +191,7 @@ define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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}
|
}
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|
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define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_cmp:
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; CHECK-LABEL: test_cmp:
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|
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%shift1 = shl i32 %rhs32, 13
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%shift1 = shl i32 %rhs32, 13
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%tst1 = icmp uge i32 %lhs32, %shift1
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%tst1 = icmp uge i32 %lhs32, %shift1
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@ -237,7 +237,7 @@ end:
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}
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}
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define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_cmn:
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; CHECK-LABEL: test_cmn:
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|
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%shift1 = shl i32 %rhs32, 13
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%shift1 = shl i32 %rhs32, 13
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%val1 = sub i32 0, %shift1
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%val1 = sub i32 0, %shift1
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@ -76,7 +76,7 @@ define void @sub_med() {
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}
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}
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define void @testing() {
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define void @testing() {
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; CHECK: testing:
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; CHECK-LABEL: testing:
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%val = load i32* @var_i32
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%val = load i32* @var_i32
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|
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; CHECK: cmp {{w[0-9]+}}, #4095
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; CHECK: cmp {{w[0-9]+}}, #4095
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@ -186,4 +186,4 @@ define void @addsub_i32rhs() {
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
|
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
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|
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ret void
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ret void
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}
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}
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@ -3,7 +3,7 @@
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declare void @use_addr(i8*)
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declare void @use_addr(i8*)
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|
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define void @test_simple_alloca(i64 %n) {
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define void @test_simple_alloca(i64 %n) {
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; CHECK: test_simple_alloca:
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; CHECK-LABEL: test_simple_alloca:
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%buf = alloca i8, i64 %n
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%buf = alloca i8, i64 %n
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; Make sure we align the stack change to 16 bytes:
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; Make sure we align the stack change to 16 bytes:
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@ -30,7 +30,7 @@ define void @test_simple_alloca(i64 %n) {
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declare void @use_addr_loc(i8*, i64*)
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declare void @use_addr_loc(i8*, i64*)
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|
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define i64 @test_alloca_with_local(i64 %n) {
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define i64 @test_alloca_with_local(i64 %n) {
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; CHECK: test_alloca_with_local:
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; CHECK-LABEL: test_alloca_with_local:
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; CHECK: sub sp, sp, #32
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; CHECK: sub sp, sp, #32
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; CHECK: stp x29, x30, [sp, #16]
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; CHECK: stp x29, x30, [sp, #16]
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@ -66,7 +66,7 @@ define i64 @test_alloca_with_local(i64 %n) {
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}
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}
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|
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define void @test_variadic_alloca(i64 %n, ...) {
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define void @test_variadic_alloca(i64 %n, ...) {
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; CHECK: test_variadic_alloca:
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; CHECK-LABEL: test_variadic_alloca:
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; CHECK: sub sp, sp, #208
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; CHECK: sub sp, sp, #208
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; CHECK: stp x29, x30, [sp, #192]
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; CHECK: stp x29, x30, [sp, #192]
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@ -89,7 +89,7 @@ define void @test_variadic_alloca(i64 %n, ...) {
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}
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}
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|
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define void @test_alloca_large_frame(i64 %n) {
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define void @test_alloca_large_frame(i64 %n) {
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; CHECK: test_alloca_large_frame:
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; CHECK-LABEL: test_alloca_large_frame:
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; CHECK: sub sp, sp, #496
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; CHECK: sub sp, sp, #496
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; CHECK: stp x29, x30, [sp, #480]
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; CHECK: stp x29, x30, [sp, #480]
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@ -11,7 +11,7 @@ declare void @test_false()
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!1 = metadata !{metadata !"branch_weights", i32 4, i32 64}
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!1 = metadata !{metadata !"branch_weights", i32 4, i32 64}
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define void @test_Bcc_fallthrough_taken(i32 %in) nounwind {
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define void @test_Bcc_fallthrough_taken(i32 %in) nounwind {
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; CHECK: test_Bcc_fallthrough_taken:
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; CHECK-LABEL: test_Bcc_fallthrough_taken:
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%tst = icmp eq i32 %in, 42
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%tst = icmp eq i32 %in, 42
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br i1 %tst, label %true, label %false, !prof !0
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br i1 %tst, label %true, label %false, !prof !0
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@ -34,7 +34,7 @@ false:
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}
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}
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define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind {
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define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind {
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; CHECK: test_Bcc_fallthrough_nottaken:
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; CHECK-LABEL: test_Bcc_fallthrough_nottaken:
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%tst = icmp eq i32 %in, 42
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%tst = icmp eq i32 %in, 42
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br i1 %tst, label %true, label %false, !prof !1
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br i1 %tst, label %true, label %false, !prof !1
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@ -57,7 +57,7 @@ false:
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}
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}
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|
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define void @test_CBZ_fallthrough_taken(i32 %in) nounwind {
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define void @test_CBZ_fallthrough_taken(i32 %in) nounwind {
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; CHECK: test_CBZ_fallthrough_taken:
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; CHECK-LABEL: test_CBZ_fallthrough_taken:
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%tst = icmp eq i32 %in, 0
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%tst = icmp eq i32 %in, 0
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br i1 %tst, label %true, label %false, !prof !0
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br i1 %tst, label %true, label %false, !prof !0
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@ -78,7 +78,7 @@ false:
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}
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}
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define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind {
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define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind {
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; CHECK: test_CBZ_fallthrough_nottaken:
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; CHECK-LABEL: test_CBZ_fallthrough_nottaken:
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%tst = icmp eq i64 %in, 0
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%tst = icmp eq i64 %in, 0
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br i1 %tst, label %true, label %false, !prof !1
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br i1 %tst, label %true, label %false, !prof !1
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|
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@ -99,7 +99,7 @@ false:
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}
|
}
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|
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define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind {
|
define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind {
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; CHECK: test_CBNZ_fallthrough_taken:
|
; CHECK-LABEL: test_CBNZ_fallthrough_taken:
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%tst = icmp ne i32 %in, 0
|
%tst = icmp ne i32 %in, 0
|
||||||
br i1 %tst, label %true, label %false, !prof !0
|
br i1 %tst, label %true, label %false, !prof !0
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|
|
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@ -120,7 +120,7 @@ false:
|
|||||||
}
|
}
|
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|
|
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define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind {
|
define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind {
|
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; CHECK: test_CBNZ_fallthrough_nottaken:
|
; CHECK-LABEL: test_CBNZ_fallthrough_nottaken:
|
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%tst = icmp ne i64 %in, 0
|
%tst = icmp ne i64 %in, 0
|
||||||
br i1 %tst, label %true, label %false, !prof !1
|
br i1 %tst, label %true, label %false, !prof !1
|
||||||
|
|
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@ -141,7 +141,7 @@ false:
|
|||||||
}
|
}
|
||||||
|
|
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define void @test_TBZ_fallthrough_taken(i32 %in) nounwind {
|
define void @test_TBZ_fallthrough_taken(i32 %in) nounwind {
|
||||||
; CHECK: test_TBZ_fallthrough_taken:
|
; CHECK-LABEL: test_TBZ_fallthrough_taken:
|
||||||
%bit = and i32 %in, 32768
|
%bit = and i32 %in, 32768
|
||||||
%tst = icmp eq i32 %bit, 0
|
%tst = icmp eq i32 %bit, 0
|
||||||
br i1 %tst, label %true, label %false, !prof !0
|
br i1 %tst, label %true, label %false, !prof !0
|
||||||
@ -163,7 +163,7 @@ false:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind {
|
define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind {
|
||||||
; CHECK: test_TBZ_fallthrough_nottaken:
|
; CHECK-LABEL: test_TBZ_fallthrough_nottaken:
|
||||||
%bit = and i64 %in, 32768
|
%bit = and i64 %in, 32768
|
||||||
%tst = icmp eq i64 %bit, 0
|
%tst = icmp eq i64 %bit, 0
|
||||||
br i1 %tst, label %true, label %false, !prof !1
|
br i1 %tst, label %true, label %false, !prof !1
|
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@ -186,7 +186,7 @@ false:
|
|||||||
|
|
||||||
|
|
||||||
define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind {
|
define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind {
|
||||||
; CHECK: test_TBNZ_fallthrough_taken:
|
; CHECK-LABEL: test_TBNZ_fallthrough_taken:
|
||||||
%bit = and i32 %in, 32768
|
%bit = and i32 %in, 32768
|
||||||
%tst = icmp ne i32 %bit, 0
|
%tst = icmp ne i32 %bit, 0
|
||||||
br i1 %tst, label %true, label %false, !prof !0
|
br i1 %tst, label %true, label %false, !prof !0
|
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@ -208,7 +208,7 @@ false:
|
|||||||
}
|
}
|
||||||
|
|
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define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind {
|
define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind {
|
||||||
; CHECK: test_TBNZ_fallthrough_nottaken:
|
; CHECK-LABEL: test_TBNZ_fallthrough_nottaken:
|
||||||
%bit = and i64 %in, 32768
|
%bit = and i64 %in, 32768
|
||||||
%tst = icmp ne i64 %bit, 0
|
%tst = icmp ne i64 %bit, 0
|
||||||
br i1 %tst, label %true, label %false, !prof !1
|
br i1 %tst, label %true, label %false, !prof !1
|
||||||
|
|||||||
@ -6,7 +6,7 @@
|
|||||||
@var64 = global i64 0
|
@var64 = global i64 0
|
||||||
|
|
||||||
define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_add_i8:
|
; CHECK-LABEL: test_atomic_load_add_i8:
|
||||||
%old = atomicrmw add i8* @var8, i8 %offset seq_cst
|
%old = atomicrmw add i8* @var8, i8 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -26,7 +26,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_add_i16:
|
; CHECK-LABEL: test_atomic_load_add_i16:
|
||||||
%old = atomicrmw add i16* @var16, i16 %offset acquire
|
%old = atomicrmw add i16* @var16, i16 %offset acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -46,7 +46,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_add_i32:
|
; CHECK-LABEL: test_atomic_load_add_i32:
|
||||||
%old = atomicrmw add i32* @var32, i32 %offset release
|
%old = atomicrmw add i32* @var32, i32 %offset release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -66,7 +66,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_add_i64:
|
; CHECK-LABEL: test_atomic_load_add_i64:
|
||||||
%old = atomicrmw add i64* @var64, i64 %offset monotonic
|
%old = atomicrmw add i64* @var64, i64 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -86,7 +86,7 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_sub_i8:
|
; CHECK-LABEL: test_atomic_load_sub_i8:
|
||||||
%old = atomicrmw sub i8* @var8, i8 %offset monotonic
|
%old = atomicrmw sub i8* @var8, i8 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -106,7 +106,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_sub_i16:
|
; CHECK-LABEL: test_atomic_load_sub_i16:
|
||||||
%old = atomicrmw sub i16* @var16, i16 %offset release
|
%old = atomicrmw sub i16* @var16, i16 %offset release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -126,7 +126,7 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_sub_i32:
|
; CHECK-LABEL: test_atomic_load_sub_i32:
|
||||||
%old = atomicrmw sub i32* @var32, i32 %offset acquire
|
%old = atomicrmw sub i32* @var32, i32 %offset acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -146,7 +146,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_sub_i64:
|
; CHECK-LABEL: test_atomic_load_sub_i64:
|
||||||
%old = atomicrmw sub i64* @var64, i64 %offset seq_cst
|
%old = atomicrmw sub i64* @var64, i64 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -166,7 +166,7 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_and_i8:
|
; CHECK-LABEL: test_atomic_load_and_i8:
|
||||||
%old = atomicrmw and i8* @var8, i8 %offset release
|
%old = atomicrmw and i8* @var8, i8 %offset release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -186,7 +186,7 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_and_i16:
|
; CHECK-LABEL: test_atomic_load_and_i16:
|
||||||
%old = atomicrmw and i16* @var16, i16 %offset monotonic
|
%old = atomicrmw and i16* @var16, i16 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -206,7 +206,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_and_i32:
|
; CHECK-LABEL: test_atomic_load_and_i32:
|
||||||
%old = atomicrmw and i32* @var32, i32 %offset seq_cst
|
%old = atomicrmw and i32* @var32, i32 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -226,7 +226,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_and_i64:
|
; CHECK-LABEL: test_atomic_load_and_i64:
|
||||||
%old = atomicrmw and i64* @var64, i64 %offset acquire
|
%old = atomicrmw and i64* @var64, i64 %offset acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -246,7 +246,7 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_or_i8:
|
; CHECK-LABEL: test_atomic_load_or_i8:
|
||||||
%old = atomicrmw or i8* @var8, i8 %offset seq_cst
|
%old = atomicrmw or i8* @var8, i8 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -266,7 +266,7 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_or_i16:
|
; CHECK-LABEL: test_atomic_load_or_i16:
|
||||||
%old = atomicrmw or i16* @var16, i16 %offset monotonic
|
%old = atomicrmw or i16* @var16, i16 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -286,7 +286,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_or_i32:
|
; CHECK-LABEL: test_atomic_load_or_i32:
|
||||||
%old = atomicrmw or i32* @var32, i32 %offset acquire
|
%old = atomicrmw or i32* @var32, i32 %offset acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -306,7 +306,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_or_i64:
|
; CHECK-LABEL: test_atomic_load_or_i64:
|
||||||
%old = atomicrmw or i64* @var64, i64 %offset release
|
%old = atomicrmw or i64* @var64, i64 %offset release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -326,7 +326,7 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_xor_i8:
|
; CHECK-LABEL: test_atomic_load_xor_i8:
|
||||||
%old = atomicrmw xor i8* @var8, i8 %offset acquire
|
%old = atomicrmw xor i8* @var8, i8 %offset acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -346,7 +346,7 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_xor_i16:
|
; CHECK-LABEL: test_atomic_load_xor_i16:
|
||||||
%old = atomicrmw xor i16* @var16, i16 %offset release
|
%old = atomicrmw xor i16* @var16, i16 %offset release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -366,7 +366,7 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_xor_i32:
|
; CHECK-LABEL: test_atomic_load_xor_i32:
|
||||||
%old = atomicrmw xor i32* @var32, i32 %offset seq_cst
|
%old = atomicrmw xor i32* @var32, i32 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -386,7 +386,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_xor_i64:
|
; CHECK-LABEL: test_atomic_load_xor_i64:
|
||||||
%old = atomicrmw xor i64* @var64, i64 %offset monotonic
|
%old = atomicrmw xor i64* @var64, i64 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -406,7 +406,7 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_xchg_i8:
|
; CHECK-LABEL: test_atomic_load_xchg_i8:
|
||||||
%old = atomicrmw xchg i8* @var8, i8 %offset monotonic
|
%old = atomicrmw xchg i8* @var8, i8 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -425,7 +425,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_xchg_i16:
|
; CHECK-LABEL: test_atomic_load_xchg_i16:
|
||||||
%old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
|
%old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -444,7 +444,7 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_xchg_i32:
|
; CHECK-LABEL: test_atomic_load_xchg_i32:
|
||||||
%old = atomicrmw xchg i32* @var32, i32 %offset release
|
%old = atomicrmw xchg i32* @var32, i32 %offset release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -463,7 +463,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_xchg_i64:
|
; CHECK-LABEL: test_atomic_load_xchg_i64:
|
||||||
%old = atomicrmw xchg i64* @var64, i64 %offset acquire
|
%old = atomicrmw xchg i64* @var64, i64 %offset acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -483,7 +483,7 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
|
|||||||
|
|
||||||
|
|
||||||
define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_min_i8:
|
; CHECK-LABEL: test_atomic_load_min_i8:
|
||||||
%old = atomicrmw min i8* @var8, i8 %offset acquire
|
%old = atomicrmw min i8* @var8, i8 %offset acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -504,7 +504,7 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_min_i16:
|
; CHECK-LABEL: test_atomic_load_min_i16:
|
||||||
%old = atomicrmw min i16* @var16, i16 %offset release
|
%old = atomicrmw min i16* @var16, i16 %offset release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -525,7 +525,7 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_min_i32:
|
; CHECK-LABEL: test_atomic_load_min_i32:
|
||||||
%old = atomicrmw min i32* @var32, i32 %offset monotonic
|
%old = atomicrmw min i32* @var32, i32 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -546,7 +546,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_min_i64:
|
; CHECK-LABEL: test_atomic_load_min_i64:
|
||||||
%old = atomicrmw min i64* @var64, i64 %offset seq_cst
|
%old = atomicrmw min i64* @var64, i64 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -567,7 +567,7 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_max_i8:
|
; CHECK-LABEL: test_atomic_load_max_i8:
|
||||||
%old = atomicrmw max i8* @var8, i8 %offset seq_cst
|
%old = atomicrmw max i8* @var8, i8 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -588,7 +588,7 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_max_i16:
|
; CHECK-LABEL: test_atomic_load_max_i16:
|
||||||
%old = atomicrmw max i16* @var16, i16 %offset acquire
|
%old = atomicrmw max i16* @var16, i16 %offset acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -609,7 +609,7 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_max_i32:
|
; CHECK-LABEL: test_atomic_load_max_i32:
|
||||||
%old = atomicrmw max i32* @var32, i32 %offset release
|
%old = atomicrmw max i32* @var32, i32 %offset release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -630,7 +630,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_max_i64:
|
; CHECK-LABEL: test_atomic_load_max_i64:
|
||||||
%old = atomicrmw max i64* @var64, i64 %offset monotonic
|
%old = atomicrmw max i64* @var64, i64 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -651,7 +651,7 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_umin_i8:
|
; CHECK-LABEL: test_atomic_load_umin_i8:
|
||||||
%old = atomicrmw umin i8* @var8, i8 %offset monotonic
|
%old = atomicrmw umin i8* @var8, i8 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -672,7 +672,7 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_umin_i16:
|
; CHECK-LABEL: test_atomic_load_umin_i16:
|
||||||
%old = atomicrmw umin i16* @var16, i16 %offset acquire
|
%old = atomicrmw umin i16* @var16, i16 %offset acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -693,7 +693,7 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_umin_i32:
|
; CHECK-LABEL: test_atomic_load_umin_i32:
|
||||||
%old = atomicrmw umin i32* @var32, i32 %offset seq_cst
|
%old = atomicrmw umin i32* @var32, i32 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -714,7 +714,7 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_umin_i64:
|
; CHECK-LABEL: test_atomic_load_umin_i64:
|
||||||
%old = atomicrmw umin i64* @var64, i64 %offset acq_rel
|
%old = atomicrmw umin i64* @var64, i64 %offset acq_rel
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -735,7 +735,7 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
|
define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_umax_i8:
|
; CHECK-LABEL: test_atomic_load_umax_i8:
|
||||||
%old = atomicrmw umax i8* @var8, i8 %offset acq_rel
|
%old = atomicrmw umax i8* @var8, i8 %offset acq_rel
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -756,7 +756,7 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
|
define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_umax_i16:
|
; CHECK-LABEL: test_atomic_load_umax_i16:
|
||||||
%old = atomicrmw umax i16* @var16, i16 %offset monotonic
|
%old = atomicrmw umax i16* @var16, i16 %offset monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -777,7 +777,7 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
|
define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_umax_i32:
|
; CHECK-LABEL: test_atomic_load_umax_i32:
|
||||||
%old = atomicrmw umax i32* @var32, i32 %offset seq_cst
|
%old = atomicrmw umax i32* @var32, i32 %offset seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -798,7 +798,7 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
|
define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
|
||||||
; CHECK: test_atomic_load_umax_i64:
|
; CHECK-LABEL: test_atomic_load_umax_i64:
|
||||||
%old = atomicrmw umax i64* @var64, i64 %offset release
|
%old = atomicrmw umax i64* @var64, i64 %offset release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -819,7 +819,7 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
|
define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
|
||||||
; CHECK: test_atomic_cmpxchg_i8:
|
; CHECK-LABEL: test_atomic_cmpxchg_i8:
|
||||||
%old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire
|
%old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -841,7 +841,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
|
define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
|
||||||
; CHECK: test_atomic_cmpxchg_i16:
|
; CHECK-LABEL: test_atomic_cmpxchg_i16:
|
||||||
%old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst
|
%old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
|
||||||
@ -863,7 +863,7 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
|
define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
|
||||||
; CHECK: test_atomic_cmpxchg_i32:
|
; CHECK-LABEL: test_atomic_cmpxchg_i32:
|
||||||
%old = cmpxchg i32* @var32, i32 %wanted, i32 %new release
|
%old = cmpxchg i32* @var32, i32 %wanted, i32 %new release
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
|
||||||
@ -885,7 +885,7 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
|
define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
|
||||||
; CHECK: test_atomic_cmpxchg_i64:
|
; CHECK-LABEL: test_atomic_cmpxchg_i64:
|
||||||
%old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic
|
%old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
|
||||||
@ -907,7 +907,7 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_monotonic_i8() nounwind {
|
define i8 @test_atomic_load_monotonic_i8() nounwind {
|
||||||
; CHECK: test_atomic_load_monotonic_i8:
|
; CHECK-LABEL: test_atomic_load_monotonic_i8:
|
||||||
%val = load atomic i8* @var8 monotonic, align 1
|
%val = load atomic i8* @var8 monotonic, align 1
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp x[[HIADDR:[0-9]+]], var8
|
; CHECK: adrp x[[HIADDR:[0-9]+]], var8
|
||||||
@ -918,7 +918,7 @@ define i8 @test_atomic_load_monotonic_i8() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
|
define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
|
||||||
; CHECK: test_atomic_load_monotonic_regoff_i8:
|
; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
|
||||||
%addr_int = add i64 %base, %off
|
%addr_int = add i64 %base, %off
|
||||||
%addr = inttoptr i64 %addr_int to i8*
|
%addr = inttoptr i64 %addr_int to i8*
|
||||||
|
|
||||||
@ -931,7 +931,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_acquire_i8() nounwind {
|
define i8 @test_atomic_load_acquire_i8() nounwind {
|
||||||
; CHECK: test_atomic_load_acquire_i8:
|
; CHECK-LABEL: test_atomic_load_acquire_i8:
|
||||||
%val = load atomic i8* @var8 acquire, align 1
|
%val = load atomic i8* @var8 acquire, align 1
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
|
||||||
@ -944,7 +944,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i8 @test_atomic_load_seq_cst_i8() nounwind {
|
define i8 @test_atomic_load_seq_cst_i8() nounwind {
|
||||||
; CHECK: test_atomic_load_seq_cst_i8:
|
; CHECK-LABEL: test_atomic_load_seq_cst_i8:
|
||||||
%val = load atomic i8* @var8 seq_cst, align 1
|
%val = load atomic i8* @var8 seq_cst, align 1
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[HIADDR:x[0-9]+]], var8
|
; CHECK: adrp [[HIADDR:x[0-9]+]], var8
|
||||||
@ -957,7 +957,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_atomic_load_monotonic_i16() nounwind {
|
define i16 @test_atomic_load_monotonic_i16() nounwind {
|
||||||
; CHECK: test_atomic_load_monotonic_i16:
|
; CHECK-LABEL: test_atomic_load_monotonic_i16:
|
||||||
%val = load atomic i16* @var16 monotonic, align 2
|
%val = load atomic i16* @var16 monotonic, align 2
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp x[[HIADDR:[0-9]+]], var16
|
; CHECK: adrp x[[HIADDR:[0-9]+]], var16
|
||||||
@ -969,7 +969,7 @@ define i16 @test_atomic_load_monotonic_i16() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
|
define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
|
||||||
; CHECK: test_atomic_load_monotonic_regoff_i32:
|
; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
|
||||||
%addr_int = add i64 %base, %off
|
%addr_int = add i64 %base, %off
|
||||||
%addr = inttoptr i64 %addr_int to i32*
|
%addr = inttoptr i64 %addr_int to i32*
|
||||||
|
|
||||||
@ -982,7 +982,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_atomic_load_seq_cst_i64() nounwind {
|
define i64 @test_atomic_load_seq_cst_i64() nounwind {
|
||||||
; CHECK: test_atomic_load_seq_cst_i64:
|
; CHECK-LABEL: test_atomic_load_seq_cst_i64:
|
||||||
%val = load atomic i64* @var64 seq_cst, align 8
|
%val = load atomic i64* @var64 seq_cst, align 8
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[HIADDR:x[0-9]+]], var64
|
; CHECK: adrp [[HIADDR:x[0-9]+]], var64
|
||||||
@ -995,7 +995,7 @@ define i64 @test_atomic_load_seq_cst_i64() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
|
define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
|
||||||
; CHECK: test_atomic_store_monotonic_i8:
|
; CHECK-LABEL: test_atomic_store_monotonic_i8:
|
||||||
store atomic i8 %val, i8* @var8 monotonic, align 1
|
store atomic i8 %val, i8* @var8 monotonic, align 1
|
||||||
; CHECK: adrp x[[HIADDR:[0-9]+]], var8
|
; CHECK: adrp x[[HIADDR:[0-9]+]], var8
|
||||||
; CHECK: strb w0, [x[[HIADDR]], #:lo12:var8]
|
; CHECK: strb w0, [x[[HIADDR]], #:lo12:var8]
|
||||||
@ -1004,7 +1004,7 @@ define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
|
define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
|
||||||
; CHECK: test_atomic_store_monotonic_regoff_i8:
|
; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
|
||||||
|
|
||||||
%addr_int = add i64 %base, %off
|
%addr_int = add i64 %base, %off
|
||||||
%addr = inttoptr i64 %addr_int to i8*
|
%addr = inttoptr i64 %addr_int to i8*
|
||||||
@ -1015,7 +1015,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val)
|
|||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
define void @test_atomic_store_release_i8(i8 %val) nounwind {
|
define void @test_atomic_store_release_i8(i8 %val) nounwind {
|
||||||
; CHECK: test_atomic_store_release_i8:
|
; CHECK-LABEL: test_atomic_store_release_i8:
|
||||||
store atomic i8 %val, i8* @var8 release, align 1
|
store atomic i8 %val, i8* @var8 release, align 1
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[HIADDR:x[0-9]+]], var8
|
; CHECK: adrp [[HIADDR:x[0-9]+]], var8
|
||||||
@ -1028,7 +1028,7 @@ define void @test_atomic_store_release_i8(i8 %val) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
|
define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
|
||||||
; CHECK: test_atomic_store_seq_cst_i8:
|
; CHECK-LABEL: test_atomic_store_seq_cst_i8:
|
||||||
store atomic i8 %val, i8* @var8 seq_cst, align 1
|
store atomic i8 %val, i8* @var8 seq_cst, align 1
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[HIADDR:x[0-9]+]], var8
|
; CHECK: adrp [[HIADDR:x[0-9]+]], var8
|
||||||
@ -1042,7 +1042,7 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
|
define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
|
||||||
; CHECK: test_atomic_store_monotonic_i16:
|
; CHECK-LABEL: test_atomic_store_monotonic_i16:
|
||||||
store atomic i16 %val, i16* @var16 monotonic, align 2
|
store atomic i16 %val, i16* @var16 monotonic, align 2
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp x[[HIADDR:[0-9]+]], var16
|
; CHECK: adrp x[[HIADDR:[0-9]+]], var16
|
||||||
@ -1053,7 +1053,7 @@ define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
|
define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
|
||||||
; CHECK: test_atomic_store_monotonic_regoff_i32:
|
; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
|
||||||
|
|
||||||
%addr_int = add i64 %base, %off
|
%addr_int = add i64 %base, %off
|
||||||
%addr = inttoptr i64 %addr_int to i32*
|
%addr = inttoptr i64 %addr_int to i32*
|
||||||
@ -1067,7 +1067,7 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_atomic_store_release_i64(i64 %val) nounwind {
|
define void @test_atomic_store_release_i64(i64 %val) nounwind {
|
||||||
; CHECK: test_atomic_store_release_i64:
|
; CHECK-LABEL: test_atomic_store_release_i64:
|
||||||
store atomic i64 %val, i64* @var64 release, align 8
|
store atomic i64 %val, i64* @var64 release, align 8
|
||||||
; CHECK-NOT: dmb
|
; CHECK-NOT: dmb
|
||||||
; CHECK: adrp [[HIADDR:x[0-9]+]], var64
|
; CHECK: adrp [[HIADDR:x[0-9]+]], var64
|
||||||
|
|||||||
@ -67,4 +67,4 @@ define void()* @get_func() {
|
|||||||
; it can relax it because it knows where get_func is. It can't!
|
; it can relax it because it knows where get_func is. It can't!
|
||||||
; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE get_func
|
; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE get_func
|
||||||
; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC get_func
|
; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC get_func
|
||||||
}
|
}
|
||||||
|
|||||||
@ -16,4 +16,4 @@ define void @test_bfi0(i32* %existing, i32* %new) {
|
|||||||
store volatile i32 %combined, i32* %existing
|
store volatile i32 %combined, i32* %existing
|
||||||
|
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -25,7 +25,7 @@ entry:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_whole32(i32* %existing, i32* %new) {
|
define void @test_whole32(i32* %existing, i32* %new) {
|
||||||
; CHECK: test_whole32:
|
; CHECK-LABEL: test_whole32:
|
||||||
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
|
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
|
||||||
|
|
||||||
%oldval = load volatile i32* %existing
|
%oldval = load volatile i32* %existing
|
||||||
@ -42,7 +42,7 @@ define void @test_whole32(i32* %existing, i32* %new) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_whole64(i64* %existing, i64* %new) {
|
define void @test_whole64(i64* %existing, i64* %new) {
|
||||||
; CHECK: test_whole64:
|
; CHECK-LABEL: test_whole64:
|
||||||
; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14
|
; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14
|
||||||
; CHECK-NOT: and
|
; CHECK-NOT: and
|
||||||
; CHECK: ret
|
; CHECK: ret
|
||||||
@ -61,7 +61,7 @@ define void @test_whole64(i64* %existing, i64* %new) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_whole32_from64(i64* %existing, i64* %new) {
|
define void @test_whole32_from64(i64* %existing, i64* %new) {
|
||||||
; CHECK: test_whole32_from64:
|
; CHECK-LABEL: test_whole32_from64:
|
||||||
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #{{0|16}}, #16
|
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #{{0|16}}, #16
|
||||||
; CHECK-NOT: and
|
; CHECK-NOT: and
|
||||||
; CHECK: ret
|
; CHECK: ret
|
||||||
@ -79,7 +79,7 @@ define void @test_whole32_from64(i64* %existing, i64* %new) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_32bit_masked(i32 *%existing, i32 *%new) {
|
define void @test_32bit_masked(i32 *%existing, i32 *%new) {
|
||||||
; CHECK: test_32bit_masked:
|
; CHECK-LABEL: test_32bit_masked:
|
||||||
; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
|
; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
|
||||||
; CHECK: and {{w[0-9]+}}, [[INSERT]], #0xff
|
; CHECK: and {{w[0-9]+}}, [[INSERT]], #0xff
|
||||||
|
|
||||||
@ -97,7 +97,7 @@ define void @test_32bit_masked(i32 *%existing, i32 *%new) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_64bit_masked(i64 *%existing, i64 *%new) {
|
define void @test_64bit_masked(i64 *%existing, i64 *%new) {
|
||||||
; CHECK: test_64bit_masked:
|
; CHECK-LABEL: test_64bit_masked:
|
||||||
; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
|
; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
|
||||||
; CHECK: and {{x[0-9]+}}, [[INSERT]], #0xffff00000000
|
; CHECK: and {{x[0-9]+}}, [[INSERT]], #0xffff00000000
|
||||||
|
|
||||||
@ -116,7 +116,7 @@ define void @test_64bit_masked(i64 *%existing, i64 *%new) {
|
|||||||
|
|
||||||
; Mask is too complicated for literal ANDwwi, make sure other avenues are tried.
|
; Mask is too complicated for literal ANDwwi, make sure other avenues are tried.
|
||||||
define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
|
define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
|
||||||
; CHECK: test_32bit_complexmask:
|
; CHECK-LABEL: test_32bit_complexmask:
|
||||||
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
|
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
|
||||||
; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||||
|
|
||||||
@ -135,7 +135,7 @@ define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
|
|||||||
|
|
||||||
; Neither mask is is a contiguous set of 1s. BFI can't be used
|
; Neither mask is is a contiguous set of 1s. BFI can't be used
|
||||||
define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
|
define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
|
||||||
; CHECK: test_32bit_badmask:
|
; CHECK-LABEL: test_32bit_badmask:
|
||||||
; CHECK-NOT: bfi
|
; CHECK-NOT: bfi
|
||||||
; CHECK: ret
|
; CHECK: ret
|
||||||
|
|
||||||
@ -154,7 +154,7 @@ define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
|
|||||||
|
|
||||||
; Ditto
|
; Ditto
|
||||||
define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
|
define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
|
||||||
; CHECK: test_64bit_badmask:
|
; CHECK-LABEL: test_64bit_badmask:
|
||||||
; CHECK-NOT: bfi
|
; CHECK-NOT: bfi
|
||||||
; CHECK: ret
|
; CHECK: ret
|
||||||
|
|
||||||
@ -174,7 +174,7 @@ define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
|
|||||||
; Bitfield insert where there's a left-over shr needed at the beginning
|
; Bitfield insert where there's a left-over shr needed at the beginning
|
||||||
; (e.g. result of str.bf1 = str.bf2)
|
; (e.g. result of str.bf1 = str.bf2)
|
||||||
define void @test_32bit_with_shr(i32* %existing, i32* %new) {
|
define void @test_32bit_with_shr(i32* %existing, i32* %new) {
|
||||||
; CHECK: test_32bit_with_shr:
|
; CHECK-LABEL: test_32bit_with_shr:
|
||||||
|
|
||||||
%oldval = load volatile i32* %existing
|
%oldval = load volatile i32* %existing
|
||||||
%oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
|
%oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
|
||||||
|
|||||||
@ -5,7 +5,7 @@
|
|||||||
@var64 = global i64 0
|
@var64 = global i64 0
|
||||||
|
|
||||||
define void @test_extendb(i8 %var) {
|
define void @test_extendb(i8 %var) {
|
||||||
; CHECK: test_extendb:
|
; CHECK-LABEL: test_extendb:
|
||||||
|
|
||||||
%sxt32 = sext i8 %var to i32
|
%sxt32 = sext i8 %var to i32
|
||||||
store volatile i32 %sxt32, i32* @var32
|
store volatile i32 %sxt32, i32* @var32
|
||||||
@ -29,7 +29,7 @@ define void @test_extendb(i8 %var) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_extendh(i16 %var) {
|
define void @test_extendh(i16 %var) {
|
||||||
; CHECK: test_extendh:
|
; CHECK-LABEL: test_extendh:
|
||||||
|
|
||||||
%sxt32 = sext i16 %var to i32
|
%sxt32 = sext i16 %var to i32
|
||||||
store volatile i32 %sxt32, i32* @var32
|
store volatile i32 %sxt32, i32* @var32
|
||||||
@ -53,7 +53,7 @@ define void @test_extendh(i16 %var) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_extendw(i32 %var) {
|
define void @test_extendw(i32 %var) {
|
||||||
; CHECK: test_extendw:
|
; CHECK-LABEL: test_extendw:
|
||||||
|
|
||||||
%sxt64 = sext i32 %var to i64
|
%sxt64 = sext i32 %var to i64
|
||||||
store volatile i64 %sxt64, i64* @var64
|
store volatile i64 %sxt64, i64* @var64
|
||||||
@ -66,7 +66,7 @@ define void @test_extendw(i32 %var) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_shifts(i32 %val32, i64 %val64) {
|
define void @test_shifts(i32 %val32, i64 %val64) {
|
||||||
; CHECK: test_shifts:
|
; CHECK-LABEL: test_shifts:
|
||||||
|
|
||||||
%shift1 = ashr i32 %val32, 31
|
%shift1 = ashr i32 %val32, 31
|
||||||
store volatile i32 %shift1, i32* @var32
|
store volatile i32 %shift1, i32* @var32
|
||||||
@ -114,7 +114,7 @@ define void @test_shifts(i32 %val32, i64 %val64) {
|
|||||||
; LLVM can produce in-register extensions taking place entirely with
|
; LLVM can produce in-register extensions taking place entirely with
|
||||||
; 64-bit registers too.
|
; 64-bit registers too.
|
||||||
define void @test_sext_inreg_64(i64 %in) {
|
define void @test_sext_inreg_64(i64 %in) {
|
||||||
; CHECK: test_sext_inreg_64:
|
; CHECK-LABEL: test_sext_inreg_64:
|
||||||
|
|
||||||
; i1 doesn't have an official alias, but crops up and is handled by
|
; i1 doesn't have an official alias, but crops up and is handled by
|
||||||
; the bitfield ops.
|
; the bitfield ops.
|
||||||
@ -143,7 +143,7 @@ define void @test_sext_inreg_64(i64 %in) {
|
|||||||
; These instructions don't actually select to official bitfield
|
; These instructions don't actually select to official bitfield
|
||||||
; operations, but it's important that we select them somehow:
|
; operations, but it's important that we select them somehow:
|
||||||
define void @test_zext_inreg_64(i64 %in) {
|
define void @test_zext_inreg_64(i64 %in) {
|
||||||
; CHECK: test_zext_inreg_64:
|
; CHECK-LABEL: test_zext_inreg_64:
|
||||||
|
|
||||||
%trunc_i8 = trunc i64 %in to i8
|
%trunc_i8 = trunc i64 %in to i8
|
||||||
%zext_i8 = zext i8 %trunc_i8 to i64
|
%zext_i8 = zext i8 %trunc_i8 to i64
|
||||||
@ -164,7 +164,7 @@ define void @test_zext_inreg_64(i64 %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_sext_inreg_from_32(i32 %in) {
|
define i64 @test_sext_inreg_from_32(i32 %in) {
|
||||||
; CHECK: test_sext_inreg_from_32:
|
; CHECK-LABEL: test_sext_inreg_from_32:
|
||||||
|
|
||||||
%small = trunc i32 %in to i1
|
%small = trunc i32 %in to i1
|
||||||
%ext = sext i1 %small to i64
|
%ext = sext i1 %small to i64
|
||||||
@ -178,7 +178,7 @@ define i64 @test_sext_inreg_from_32(i32 %in) {
|
|||||||
|
|
||||||
|
|
||||||
define i32 @test_ubfx32(i32* %addr) {
|
define i32 @test_ubfx32(i32* %addr) {
|
||||||
; CHECK: test_ubfx32:
|
; CHECK-LABEL: test_ubfx32:
|
||||||
; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
|
; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
|
||||||
|
|
||||||
%fields = load i32* %addr
|
%fields = load i32* %addr
|
||||||
@ -188,7 +188,7 @@ define i32 @test_ubfx32(i32* %addr) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_ubfx64(i64* %addr) {
|
define i64 @test_ubfx64(i64* %addr) {
|
||||||
; CHECK: test_ubfx64:
|
; CHECK-LABEL: test_ubfx64:
|
||||||
; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
|
; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
|
||||||
|
|
||||||
%fields = load i64* %addr
|
%fields = load i64* %addr
|
||||||
@ -198,7 +198,7 @@ define i64 @test_ubfx64(i64* %addr) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_sbfx32(i32* %addr) {
|
define i32 @test_sbfx32(i32* %addr) {
|
||||||
; CHECK: test_sbfx32:
|
; CHECK-LABEL: test_sbfx32:
|
||||||
; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
|
; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
|
||||||
|
|
||||||
%fields = load i32* %addr
|
%fields = load i32* %addr
|
||||||
@ -208,7 +208,7 @@ define i32 @test_sbfx32(i32* %addr) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_sbfx64(i64* %addr) {
|
define i64 @test_sbfx64(i64* %addr) {
|
||||||
; CHECK: test_sbfx64:
|
; CHECK-LABEL: test_sbfx64:
|
||||||
; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63
|
; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63
|
||||||
|
|
||||||
%fields = load i64* %addr
|
%fields = load i64* %addr
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@addr = global i8* null
|
@addr = global i8* null
|
||||||
|
|
||||||
define void @test_blockaddress() {
|
define void @test_blockaddress() {
|
||||||
; CHECK: test_blockaddress:
|
; CHECK-LABEL: test_blockaddress:
|
||||||
store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
|
store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
|
||||||
%val = load volatile i8** @addr
|
%val = load volatile i8** @addr
|
||||||
indirectbr i8* %val, [label %block]
|
indirectbr i8* %val, [label %block]
|
||||||
|
|||||||
@ -35,4 +35,4 @@ test5:
|
|||||||
|
|
||||||
end:
|
end:
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@var64 = global i64 0
|
@var64 = global i64 0
|
||||||
|
|
||||||
define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
||||||
; CHECK: test_csel:
|
; CHECK-LABEL: test_csel:
|
||||||
|
|
||||||
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
||||||
%val1 = select i1 %tst1, i32 42, i32 52
|
%val1 = select i1 %tst1, i32 42, i32 52
|
||||||
@ -26,7 +26,7 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) {
|
define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) {
|
||||||
; CHECK: test_floatcsel:
|
; CHECK-LABEL: test_floatcsel:
|
||||||
|
|
||||||
%tst1 = fcmp one float %lhs32, %rhs32
|
%tst1 = fcmp one float %lhs32, %rhs32
|
||||||
; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
|
; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
|
||||||
@ -53,7 +53,7 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r
|
|||||||
|
|
||||||
|
|
||||||
define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
||||||
; CHECK: test_csinc:
|
; CHECK-LABEL: test_csinc:
|
||||||
|
|
||||||
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
|
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
|
||||||
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
||||||
@ -93,7 +93,7 @@ define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
||||||
; CHECK: test_csinv:
|
; CHECK-LABEL: test_csinv:
|
||||||
|
|
||||||
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
|
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
|
||||||
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
||||||
@ -133,7 +133,7 @@ define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
||||||
; CHECK: test_csneg:
|
; CHECK-LABEL: test_csneg:
|
||||||
|
|
||||||
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
|
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
|
||||||
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
||||||
@ -173,7 +173,7 @@ define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
|
define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
|
||||||
; CHECK: test_cset:
|
; CHECK-LABEL: test_cset:
|
||||||
|
|
||||||
; N.b. code is not optimal here (32-bit csinc would be better) but
|
; N.b. code is not optimal here (32-bit csinc would be better) but
|
||||||
; incoming DAG is too complex
|
; incoming DAG is too complex
|
||||||
@ -194,7 +194,7 @@ define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
|
define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
|
||||||
; CHECK: test_csetm:
|
; CHECK-LABEL: test_csetm:
|
||||||
|
|
||||||
%tst1 = icmp eq i32 %lhs, %rhs
|
%tst1 = icmp eq i32 %lhs, %rhs
|
||||||
%val1 = sext i1 %tst1 to i32
|
%val1 = sext i1 %tst1 to i32
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
||||||
|
|
||||||
define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
|
define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
|
||||||
; CHECK: test_select_i32:
|
; CHECK-LABEL: test_select_i32:
|
||||||
%val = select i1 %bit, i32 %a, i32 %b
|
%val = select i1 %bit, i32 %a, i32 %b
|
||||||
; CHECK: movz [[ONE:w[0-9]+]], #1
|
; CHECK: movz [[ONE:w[0-9]+]], #1
|
||||||
; CHECK: tst w0, [[ONE]]
|
; CHECK: tst w0, [[ONE]]
|
||||||
@ -11,7 +11,7 @@ define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
|
define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
|
||||||
; CHECK: test_select_i64:
|
; CHECK-LABEL: test_select_i64:
|
||||||
%val = select i1 %bit, i64 %a, i64 %b
|
%val = select i1 %bit, i64 %a, i64 %b
|
||||||
; CHECK: movz [[ONE:w[0-9]+]], #1
|
; CHECK: movz [[ONE:w[0-9]+]], #1
|
||||||
; CHECK: tst w0, [[ONE]]
|
; CHECK: tst w0, [[ONE]]
|
||||||
@ -21,7 +21,7 @@ define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define float @test_select_float(i1 %bit, float %a, float %b) {
|
define float @test_select_float(i1 %bit, float %a, float %b) {
|
||||||
; CHECK: test_select_float:
|
; CHECK-LABEL: test_select_float:
|
||||||
%val = select i1 %bit, float %a, float %b
|
%val = select i1 %bit, float %a, float %b
|
||||||
; CHECK: movz [[ONE:w[0-9]+]], #1
|
; CHECK: movz [[ONE:w[0-9]+]], #1
|
||||||
; CHECK: tst w0, [[ONE]]
|
; CHECK: tst w0, [[ONE]]
|
||||||
@ -31,7 +31,7 @@ define float @test_select_float(i1 %bit, float %a, float %b) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define double @test_select_double(i1 %bit, double %a, double %b) {
|
define double @test_select_double(i1 %bit, double %a, double %b) {
|
||||||
; CHECK: test_select_double:
|
; CHECK-LABEL: test_select_double:
|
||||||
%val = select i1 %bit, double %a, double %b
|
%val = select i1 %bit, double %a, double %b
|
||||||
; CHECK: movz [[ONE:w[0-9]+]], #1
|
; CHECK: movz [[ONE:w[0-9]+]], #1
|
||||||
; CHECK: tst w0, [[ONE]]
|
; CHECK: tst w0, [[ONE]]
|
||||||
@ -41,7 +41,7 @@ define double @test_select_double(i1 %bit, double %a, double %b) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_brcond(i1 %bit) {
|
define i32 @test_brcond(i1 %bit) {
|
||||||
; CHECK: test_brcond:
|
; CHECK-LABEL: test_brcond:
|
||||||
br i1 %bit, label %true, label %false
|
br i1 %bit, label %true, label %false
|
||||||
; CHECK: tbz {{w[0-9]+}}, #0, .LBB
|
; CHECK: tbz {{w[0-9]+}}, #0, .LBB
|
||||||
|
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
||||||
|
|
||||||
define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
|
define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
|
||||||
; CHECK: test_madd32:
|
; CHECK-LABEL: test_madd32:
|
||||||
%mid = mul i32 %val1, %val2
|
%mid = mul i32 %val1, %val2
|
||||||
%res = add i32 %val0, %mid
|
%res = add i32 %val0, %mid
|
||||||
; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||||
@ -9,7 +9,7 @@ define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
|
define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
|
||||||
; CHECK: test_madd64:
|
; CHECK-LABEL: test_madd64:
|
||||||
%mid = mul i64 %val1, %val2
|
%mid = mul i64 %val1, %val2
|
||||||
%res = add i64 %val0, %mid
|
%res = add i64 %val0, %mid
|
||||||
; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||||
@ -17,7 +17,7 @@ define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
|
define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
|
||||||
; CHECK: test_msub32:
|
; CHECK-LABEL: test_msub32:
|
||||||
%mid = mul i32 %val1, %val2
|
%mid = mul i32 %val1, %val2
|
||||||
%res = sub i32 %val0, %mid
|
%res = sub i32 %val0, %mid
|
||||||
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||||
@ -25,7 +25,7 @@ define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
|
define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
|
||||||
; CHECK: test_msub64:
|
; CHECK-LABEL: test_msub64:
|
||||||
%mid = mul i64 %val1, %val2
|
%mid = mul i64 %val1, %val2
|
||||||
%res = sub i64 %val0, %mid
|
%res = sub i64 %val0, %mid
|
||||||
; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||||
@ -33,7 +33,7 @@ define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
|
define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
|
||||||
; CHECK: test_smaddl:
|
; CHECK-LABEL: test_smaddl:
|
||||||
%ext1 = sext i32 %val1 to i64
|
%ext1 = sext i32 %val1 to i64
|
||||||
%ext2 = sext i32 %val2 to i64
|
%ext2 = sext i32 %val2 to i64
|
||||||
%prod = mul i64 %ext1, %ext2
|
%prod = mul i64 %ext1, %ext2
|
||||||
@ -43,7 +43,7 @@ define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
|
define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
|
||||||
; CHECK: test_smsubl:
|
; CHECK-LABEL: test_smsubl:
|
||||||
%ext1 = sext i32 %val1 to i64
|
%ext1 = sext i32 %val1 to i64
|
||||||
%ext2 = sext i32 %val2 to i64
|
%ext2 = sext i32 %val2 to i64
|
||||||
%prod = mul i64 %ext1, %ext2
|
%prod = mul i64 %ext1, %ext2
|
||||||
@ -53,7 +53,7 @@ define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
|
define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
|
||||||
; CHECK: test_umaddl:
|
; CHECK-LABEL: test_umaddl:
|
||||||
%ext1 = zext i32 %val1 to i64
|
%ext1 = zext i32 %val1 to i64
|
||||||
%ext2 = zext i32 %val2 to i64
|
%ext2 = zext i32 %val2 to i64
|
||||||
%prod = mul i64 %ext1, %ext2
|
%prod = mul i64 %ext1, %ext2
|
||||||
@ -63,7 +63,7 @@ define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
|
define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
|
||||||
; CHECK: test_umsubl:
|
; CHECK-LABEL: test_umsubl:
|
||||||
%ext1 = zext i32 %val1 to i64
|
%ext1 = zext i32 %val1 to i64
|
||||||
%ext2 = zext i32 %val2 to i64
|
%ext2 = zext i32 %val2 to i64
|
||||||
%prod = mul i64 %ext1, %ext2
|
%prod = mul i64 %ext1, %ext2
|
||||||
@ -73,7 +73,7 @@ define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_smulh(i64 %lhs, i64 %rhs) {
|
define i64 @test_smulh(i64 %lhs, i64 %rhs) {
|
||||||
; CHECK: test_smulh:
|
; CHECK-LABEL: test_smulh:
|
||||||
%ext1 = sext i64 %lhs to i128
|
%ext1 = sext i64 %lhs to i128
|
||||||
%ext2 = sext i64 %rhs to i128
|
%ext2 = sext i64 %rhs to i128
|
||||||
%res = mul i128 %ext1, %ext2
|
%res = mul i128 %ext1, %ext2
|
||||||
@ -84,7 +84,7 @@ define i64 @test_smulh(i64 %lhs, i64 %rhs) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_umulh(i64 %lhs, i64 %rhs) {
|
define i64 @test_umulh(i64 %lhs, i64 %rhs) {
|
||||||
; CHECK: test_umulh:
|
; CHECK-LABEL: test_umulh:
|
||||||
%ext1 = zext i64 %lhs to i128
|
%ext1 = zext i64 %lhs to i128
|
||||||
%ext2 = zext i64 %rhs to i128
|
%ext2 = zext i64 %rhs to i128
|
||||||
%res = mul i128 %ext1, %ext2
|
%res = mul i128 %ext1, %ext2
|
||||||
@ -95,21 +95,21 @@ define i64 @test_umulh(i64 %lhs, i64 %rhs) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_mul32(i32 %lhs, i32 %rhs) {
|
define i32 @test_mul32(i32 %lhs, i32 %rhs) {
|
||||||
; CHECK: test_mul32:
|
; CHECK-LABEL: test_mul32:
|
||||||
%res = mul i32 %lhs, %rhs
|
%res = mul i32 %lhs, %rhs
|
||||||
; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||||
ret i32 %res
|
ret i32 %res
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_mul64(i64 %lhs, i64 %rhs) {
|
define i64 @test_mul64(i64 %lhs, i64 %rhs) {
|
||||||
; CHECK: test_mul64:
|
; CHECK-LABEL: test_mul64:
|
||||||
%res = mul i64 %lhs, %rhs
|
%res = mul i64 %lhs, %rhs
|
||||||
; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||||
ret i64 %res
|
ret i64 %res
|
||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
|
define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
|
||||||
; CHECK: test_mneg32:
|
; CHECK-LABEL: test_mneg32:
|
||||||
%prod = mul i32 %lhs, %rhs
|
%prod = mul i32 %lhs, %rhs
|
||||||
%res = sub i32 0, %prod
|
%res = sub i32 0, %prod
|
||||||
; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||||
@ -117,7 +117,7 @@ define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
|
define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
|
||||||
; CHECK: test_mneg64:
|
; CHECK-LABEL: test_mneg64:
|
||||||
%prod = mul i64 %lhs, %rhs
|
%prod = mul i64 %lhs, %rhs
|
||||||
%res = sub i64 0, %prod
|
%res = sub i64 0, %prod
|
||||||
; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||||
@ -125,7 +125,7 @@ define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_smull(i32 %lhs, i32 %rhs) {
|
define i64 @test_smull(i32 %lhs, i32 %rhs) {
|
||||||
; CHECK: test_smull:
|
; CHECK-LABEL: test_smull:
|
||||||
%ext1 = sext i32 %lhs to i64
|
%ext1 = sext i32 %lhs to i64
|
||||||
%ext2 = sext i32 %rhs to i64
|
%ext2 = sext i32 %rhs to i64
|
||||||
%res = mul i64 %ext1, %ext2
|
%res = mul i64 %ext1, %ext2
|
||||||
@ -134,7 +134,7 @@ define i64 @test_smull(i32 %lhs, i32 %rhs) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_umull(i32 %lhs, i32 %rhs) {
|
define i64 @test_umull(i32 %lhs, i32 %rhs) {
|
||||||
; CHECK: test_umull:
|
; CHECK-LABEL: test_umull:
|
||||||
%ext1 = zext i32 %lhs to i64
|
%ext1 = zext i32 %lhs to i64
|
||||||
%ext2 = zext i32 %rhs to i64
|
%ext2 = zext i32 %rhs to i64
|
||||||
%res = mul i64 %ext1, %ext2
|
%res = mul i64 %ext1, %ext2
|
||||||
@ -143,7 +143,7 @@ define i64 @test_umull(i32 %lhs, i32 %rhs) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
|
define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
|
||||||
; CHECK: test_smnegl:
|
; CHECK-LABEL: test_smnegl:
|
||||||
%ext1 = sext i32 %lhs to i64
|
%ext1 = sext i32 %lhs to i64
|
||||||
%ext2 = sext i32 %rhs to i64
|
%ext2 = sext i32 %rhs to i64
|
||||||
%prod = mul i64 %ext1, %ext2
|
%prod = mul i64 %ext1, %ext2
|
||||||
@ -153,7 +153,7 @@ define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_umnegl(i32 %lhs, i32 %rhs) {
|
define i64 @test_umnegl(i32 %lhs, i32 %rhs) {
|
||||||
; CHECK: test_umnegl:
|
; CHECK-LABEL: test_umnegl:
|
||||||
%ext1 = zext i32 %lhs to i64
|
%ext1 = zext i32 %lhs to i64
|
||||||
%ext2 = zext i32 %rhs to i64
|
%ext2 = zext i32 %rhs to i64
|
||||||
%prod = mul i64 %ext1, %ext2
|
%prod = mul i64 %ext1, %ext2
|
||||||
|
|||||||
@ -139,7 +139,7 @@ define void @udiv_i32() {
|
|||||||
; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
|
; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
|
||||||
; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.
|
; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.
|
||||||
define i32 @test_lsl32() {
|
define i32 @test_lsl32() {
|
||||||
; CHECK: test_lsl32:
|
; CHECK-LABEL: test_lsl32:
|
||||||
|
|
||||||
%val = load i32* @var32_0
|
%val = load i32* @var32_0
|
||||||
%ret = shl i32 1, %val
|
%ret = shl i32 1, %val
|
||||||
@ -149,7 +149,7 @@ define i32 @test_lsl32() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_lsr32() {
|
define i32 @test_lsr32() {
|
||||||
; CHECK: test_lsr32:
|
; CHECK-LABEL: test_lsr32:
|
||||||
|
|
||||||
%val = load i32* @var32_0
|
%val = load i32* @var32_0
|
||||||
%ret = lshr i32 1, %val
|
%ret = lshr i32 1, %val
|
||||||
@ -159,7 +159,7 @@ define i32 @test_lsr32() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_asr32(i32 %in) {
|
define i32 @test_asr32(i32 %in) {
|
||||||
; CHECK: test_asr32:
|
; CHECK-LABEL: test_asr32:
|
||||||
|
|
||||||
%val = load i32* @var32_0
|
%val = load i32* @var32_0
|
||||||
%ret = ashr i32 %in, %val
|
%ret = ashr i32 %in, %val
|
||||||
|
|||||||
@ -51,4 +51,4 @@ define i32* @wibble() {
|
|||||||
; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
|
; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
|
||||||
; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
|
; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
|
||||||
; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
|
; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
|
||||||
}
|
}
|
||||||
|
|||||||
@ -3,7 +3,7 @@
|
|||||||
declare void @bar(i32)
|
declare void @bar(i32)
|
||||||
|
|
||||||
define void @test_float(float %a, float %b) {
|
define void @test_float(float %a, float %b) {
|
||||||
; CHECK: test_float:
|
; CHECK-LABEL: test_float:
|
||||||
|
|
||||||
%tst1 = fcmp oeq float %a, %b
|
%tst1 = fcmp oeq float %a, %b
|
||||||
br i1 %tst1, label %end, label %t2
|
br i1 %tst1, label %end, label %t2
|
||||||
@ -42,7 +42,7 @@ end:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_double(double %a, double %b) {
|
define void @test_double(double %a, double %b) {
|
||||||
; CHECK: test_double:
|
; CHECK-LABEL: test_double:
|
||||||
|
|
||||||
%tst1 = fcmp oeq double %a, %b
|
%tst1 = fcmp oeq double %a, %b
|
||||||
br i1 %tst1, label %end, label %t2
|
br i1 %tst1, label %end, label %t2
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@var64 = global i64 0
|
@var64 = global i64 0
|
||||||
|
|
||||||
define void @test_fcvtzs(float %flt, double %dbl) {
|
define void @test_fcvtzs(float %flt, double %dbl) {
|
||||||
; CHECK: test_fcvtzs:
|
; CHECK-LABEL: test_fcvtzs:
|
||||||
|
|
||||||
%fix1 = fmul float %flt, 128.0
|
%fix1 = fmul float %flt, 128.0
|
||||||
%cvt1 = fptosi float %fix1 to i32
|
%cvt1 = fptosi float %fix1 to i32
|
||||||
@ -50,7 +50,7 @@ define void @test_fcvtzs(float %flt, double %dbl) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_fcvtzu(float %flt, double %dbl) {
|
define void @test_fcvtzu(float %flt, double %dbl) {
|
||||||
; CHECK: test_fcvtzu:
|
; CHECK-LABEL: test_fcvtzu:
|
||||||
|
|
||||||
%fix1 = fmul float %flt, 128.0
|
%fix1 = fmul float %flt, 128.0
|
||||||
%cvt1 = fptoui float %fix1 to i32
|
%cvt1 = fptoui float %fix1 to i32
|
||||||
@ -99,7 +99,7 @@ define void @test_fcvtzu(float %flt, double %dbl) {
|
|||||||
@vardouble = global double 0.0
|
@vardouble = global double 0.0
|
||||||
|
|
||||||
define void @test_scvtf(i32 %int, i64 %long) {
|
define void @test_scvtf(i32 %int, i64 %long) {
|
||||||
; CHECK: test_scvtf:
|
; CHECK-LABEL: test_scvtf:
|
||||||
|
|
||||||
%cvt1 = sitofp i32 %int to float
|
%cvt1 = sitofp i32 %int to float
|
||||||
%fix1 = fdiv float %cvt1, 128.0
|
%fix1 = fdiv float %cvt1, 128.0
|
||||||
@ -145,7 +145,7 @@ define void @test_scvtf(i32 %int, i64 %long) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_ucvtf(i32 %int, i64 %long) {
|
define void @test_ucvtf(i32 %int, i64 %long) {
|
||||||
; CHECK: test_ucvtf:
|
; CHECK-LABEL: test_ucvtf:
|
||||||
|
|
||||||
%cvt1 = uitofp i32 %int to float
|
%cvt1 = uitofp i32 %int to float
|
||||||
%fix1 = fdiv float %cvt1, 128.0
|
%fix1 = fdiv float %cvt1, 128.0
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
||||||
|
|
||||||
define i32 @test_floattoi32(float %in) {
|
define i32 @test_floattoi32(float %in) {
|
||||||
; CHECK: test_floattoi32:
|
; CHECK-LABEL: test_floattoi32:
|
||||||
|
|
||||||
%signed = fptosi float %in to i32
|
%signed = fptosi float %in to i32
|
||||||
%unsigned = fptoui float %in to i32
|
%unsigned = fptoui float %in to i32
|
||||||
@ -16,7 +16,7 @@ define i32 @test_floattoi32(float %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_doubletoi32(double %in) {
|
define i32 @test_doubletoi32(double %in) {
|
||||||
; CHECK: test_doubletoi32:
|
; CHECK-LABEL: test_doubletoi32:
|
||||||
|
|
||||||
%signed = fptosi double %in to i32
|
%signed = fptosi double %in to i32
|
||||||
%unsigned = fptoui double %in to i32
|
%unsigned = fptoui double %in to i32
|
||||||
@ -31,7 +31,7 @@ define i32 @test_doubletoi32(double %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_floattoi64(float %in) {
|
define i64 @test_floattoi64(float %in) {
|
||||||
; CHECK: test_floattoi64:
|
; CHECK-LABEL: test_floattoi64:
|
||||||
|
|
||||||
%signed = fptosi float %in to i64
|
%signed = fptosi float %in to i64
|
||||||
%unsigned = fptoui float %in to i64
|
%unsigned = fptoui float %in to i64
|
||||||
@ -46,7 +46,7 @@ define i64 @test_floattoi64(float %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_doubletoi64(double %in) {
|
define i64 @test_doubletoi64(double %in) {
|
||||||
; CHECK: test_doubletoi64:
|
; CHECK-LABEL: test_doubletoi64:
|
||||||
|
|
||||||
%signed = fptosi double %in to i64
|
%signed = fptosi double %in to i64
|
||||||
%unsigned = fptoui double %in to i64
|
%unsigned = fptoui double %in to i64
|
||||||
@ -61,7 +61,7 @@ define i64 @test_doubletoi64(double %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define float @test_i32tofloat(i32 %in) {
|
define float @test_i32tofloat(i32 %in) {
|
||||||
; CHECK: test_i32tofloat:
|
; CHECK-LABEL: test_i32tofloat:
|
||||||
|
|
||||||
%signed = sitofp i32 %in to float
|
%signed = sitofp i32 %in to float
|
||||||
%unsigned = uitofp i32 %in to float
|
%unsigned = uitofp i32 %in to float
|
||||||
@ -75,7 +75,7 @@ define float @test_i32tofloat(i32 %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define double @test_i32todouble(i32 %in) {
|
define double @test_i32todouble(i32 %in) {
|
||||||
; CHECK: test_i32todouble:
|
; CHECK-LABEL: test_i32todouble:
|
||||||
|
|
||||||
%signed = sitofp i32 %in to double
|
%signed = sitofp i32 %in to double
|
||||||
%unsigned = uitofp i32 %in to double
|
%unsigned = uitofp i32 %in to double
|
||||||
@ -89,7 +89,7 @@ define double @test_i32todouble(i32 %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define float @test_i64tofloat(i64 %in) {
|
define float @test_i64tofloat(i64 %in) {
|
||||||
; CHECK: test_i64tofloat:
|
; CHECK-LABEL: test_i64tofloat:
|
||||||
|
|
||||||
%signed = sitofp i64 %in to float
|
%signed = sitofp i64 %in to float
|
||||||
%unsigned = uitofp i64 %in to float
|
%unsigned = uitofp i64 %in to float
|
||||||
@ -103,7 +103,7 @@ define float @test_i64tofloat(i64 %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define double @test_i64todouble(i64 %in) {
|
define double @test_i64todouble(i64 %in) {
|
||||||
; CHECK: test_i64todouble:
|
; CHECK-LABEL: test_i64todouble:
|
||||||
|
|
||||||
%signed = sitofp i64 %in to double
|
%signed = sitofp i64 %in to double
|
||||||
%unsigned = uitofp i64 %in to double
|
%unsigned = uitofp i64 %in to double
|
||||||
@ -117,7 +117,7 @@ define double @test_i64todouble(i64 %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_bitcastfloattoi32(float %in) {
|
define i32 @test_bitcastfloattoi32(float %in) {
|
||||||
; CHECK: test_bitcastfloattoi32:
|
; CHECK-LABEL: test_bitcastfloattoi32:
|
||||||
|
|
||||||
%res = bitcast float %in to i32
|
%res = bitcast float %in to i32
|
||||||
; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}}
|
; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}}
|
||||||
@ -125,7 +125,7 @@ define i32 @test_bitcastfloattoi32(float %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_bitcastdoubletoi64(double %in) {
|
define i64 @test_bitcastdoubletoi64(double %in) {
|
||||||
; CHECK: test_bitcastdoubletoi64:
|
; CHECK-LABEL: test_bitcastdoubletoi64:
|
||||||
|
|
||||||
%res = bitcast double %in to i64
|
%res = bitcast double %in to i64
|
||||||
; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
|
; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
|
||||||
@ -133,7 +133,7 @@ define i64 @test_bitcastdoubletoi64(double %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define float @test_bitcasti32tofloat(i32 %in) {
|
define float @test_bitcasti32tofloat(i32 %in) {
|
||||||
; CHECK: test_bitcasti32tofloat:
|
; CHECK-LABEL: test_bitcasti32tofloat:
|
||||||
|
|
||||||
%res = bitcast i32 %in to float
|
%res = bitcast i32 %in to float
|
||||||
; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}}
|
; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}}
|
||||||
@ -142,7 +142,7 @@ define float @test_bitcasti32tofloat(i32 %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define double @test_bitcasti64todouble(i64 %in) {
|
define double @test_bitcasti64todouble(i64 %in) {
|
||||||
; CHECK: test_bitcasti64todouble:
|
; CHECK-LABEL: test_bitcasti64todouble:
|
||||||
|
|
||||||
%res = bitcast i64 %in to double
|
%res = bitcast i64 %in to double
|
||||||
; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
|
; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
|
||||||
|
|||||||
@ -9,7 +9,7 @@ declare void @bar()
|
|||||||
@var = global i32 0
|
@var = global i32 0
|
||||||
|
|
||||||
define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
|
define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
|
||||||
; CHECK: test_multiflag:
|
; CHECK-LABEL: test_multiflag:
|
||||||
|
|
||||||
%test = icmp ne i32 %n, %m
|
%test = icmp ne i32 %n, %m
|
||||||
; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
|
; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@vardouble = global double 0.0
|
@vardouble = global double 0.0
|
||||||
|
|
||||||
define void @testfloat() {
|
define void @testfloat() {
|
||||||
; CHECK: testfloat:
|
; CHECK-LABEL: testfloat:
|
||||||
%val1 = load float* @varfloat
|
%val1 = load float* @varfloat
|
||||||
|
|
||||||
%val2 = fadd float %val1, %val1
|
%val2 = fadd float %val1, %val1
|
||||||
@ -32,7 +32,7 @@ define void @testfloat() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @testdouble() {
|
define void @testdouble() {
|
||||||
; CHECK: testdouble:
|
; CHECK-LABEL: testdouble:
|
||||||
%val1 = load double* @vardouble
|
%val1 = load double* @vardouble
|
||||||
|
|
||||||
%val2 = fadd double %val1, %val1
|
%val2 = fadd double %val1, %val1
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@vardouble = global double 0.0
|
@vardouble = global double 0.0
|
||||||
|
|
||||||
define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
|
||||||
; CHECK: test_csel:
|
; CHECK-LABEL: test_csel:
|
||||||
|
|
||||||
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
%tst1 = icmp ugt i32 %lhs32, %rhs32
|
||||||
%val1 = select i1 %tst1, float 0.0, float 1.0
|
%val1 = select i1 %tst1, float 0.0, float 1.0
|
||||||
|
|||||||
@ -45,7 +45,7 @@ define float @test_fnmsub(float %a, float %b, float %c) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define double @testd_fmadd(double %a, double %b, double %c) {
|
define double @testd_fmadd(double %a, double %b, double %c) {
|
||||||
; CHECK: testd_fmadd:
|
; CHECK-LABEL: testd_fmadd:
|
||||||
; CHECK-NOFAST: testd_fmadd:
|
; CHECK-NOFAST: testd_fmadd:
|
||||||
%val = call double @llvm.fma.f64(double %a, double %b, double %c)
|
%val = call double @llvm.fma.f64(double %a, double %b, double %c)
|
||||||
; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
||||||
@ -54,7 +54,7 @@ define double @testd_fmadd(double %a, double %b, double %c) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define double @testd_fmsub(double %a, double %b, double %c) {
|
define double @testd_fmsub(double %a, double %b, double %c) {
|
||||||
; CHECK: testd_fmsub:
|
; CHECK-LABEL: testd_fmsub:
|
||||||
; CHECK-NOFAST: testd_fmsub:
|
; CHECK-NOFAST: testd_fmsub:
|
||||||
%nega = fsub double -0.0, %a
|
%nega = fsub double -0.0, %a
|
||||||
%val = call double @llvm.fma.f64(double %nega, double %b, double %c)
|
%val = call double @llvm.fma.f64(double %nega, double %b, double %c)
|
||||||
@ -64,7 +64,7 @@ define double @testd_fmsub(double %a, double %b, double %c) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define double @testd_fnmadd(double %a, double %b, double %c) {
|
define double @testd_fnmadd(double %a, double %b, double %c) {
|
||||||
; CHECK: testd_fnmadd:
|
; CHECK-LABEL: testd_fnmadd:
|
||||||
; CHECK-NOFAST: testd_fnmadd:
|
; CHECK-NOFAST: testd_fnmadd:
|
||||||
%negc = fsub double -0.0, %c
|
%negc = fsub double -0.0, %c
|
||||||
%val = call double @llvm.fma.f64(double %a, double %b, double %negc)
|
%val = call double @llvm.fma.f64(double %a, double %b, double %negc)
|
||||||
@ -74,7 +74,7 @@ define double @testd_fnmadd(double %a, double %b, double %c) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define double @testd_fnmsub(double %a, double %b, double %c) {
|
define double @testd_fnmsub(double %a, double %b, double %c) {
|
||||||
; CHECK: testd_fnmsub:
|
; CHECK-LABEL: testd_fnmsub:
|
||||||
; CHECK-NOFAST: testd_fnmsub:
|
; CHECK-NOFAST: testd_fnmsub:
|
||||||
%nega = fsub double -0.0, %a
|
%nega = fsub double -0.0, %a
|
||||||
%negc = fsub double -0.0, %c
|
%negc = fsub double -0.0, %c
|
||||||
|
|||||||
@ -5,7 +5,7 @@ declare void @bar(i8*, i8*, i32*)
|
|||||||
; which is not supported.
|
; which is not supported.
|
||||||
|
|
||||||
define fp128 @test_folding() {
|
define fp128 @test_folding() {
|
||||||
; CHECK: test_folding:
|
; CHECK-LABEL: test_folding:
|
||||||
%l = alloca i32
|
%l = alloca i32
|
||||||
store i32 42, i32* %l
|
store i32 42, i32* %l
|
||||||
%val = load i32* %l
|
%val = load i32* %l
|
||||||
@ -14,4 +14,4 @@ define fp128 @test_folding() {
|
|||||||
; successfully.
|
; successfully.
|
||||||
; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI
|
; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI
|
||||||
ret fp128 %fpval
|
ret fp128 %fpval
|
||||||
}
|
}
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@rhs = global fp128 zeroinitializer
|
@rhs = global fp128 zeroinitializer
|
||||||
|
|
||||||
define fp128 @test_add() {
|
define fp128 @test_add() {
|
||||||
; CHECK: test_add:
|
; CHECK-LABEL: test_add:
|
||||||
|
|
||||||
%lhs = load fp128* @lhs
|
%lhs = load fp128* @lhs
|
||||||
%rhs = load fp128* @rhs
|
%rhs = load fp128* @rhs
|
||||||
@ -17,7 +17,7 @@ define fp128 @test_add() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define fp128 @test_sub() {
|
define fp128 @test_sub() {
|
||||||
; CHECK: test_sub:
|
; CHECK-LABEL: test_sub:
|
||||||
|
|
||||||
%lhs = load fp128* @lhs
|
%lhs = load fp128* @lhs
|
||||||
%rhs = load fp128* @rhs
|
%rhs = load fp128* @rhs
|
||||||
@ -30,7 +30,7 @@ define fp128 @test_sub() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define fp128 @test_mul() {
|
define fp128 @test_mul() {
|
||||||
; CHECK: test_mul:
|
; CHECK-LABEL: test_mul:
|
||||||
|
|
||||||
%lhs = load fp128* @lhs
|
%lhs = load fp128* @lhs
|
||||||
%rhs = load fp128* @rhs
|
%rhs = load fp128* @rhs
|
||||||
@ -43,7 +43,7 @@ define fp128 @test_mul() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define fp128 @test_div() {
|
define fp128 @test_div() {
|
||||||
; CHECK: test_div:
|
; CHECK-LABEL: test_div:
|
||||||
|
|
||||||
%lhs = load fp128* @lhs
|
%lhs = load fp128* @lhs
|
||||||
%rhs = load fp128* @rhs
|
%rhs = load fp128* @rhs
|
||||||
@ -59,7 +59,7 @@ define fp128 @test_div() {
|
|||||||
@var64 = global i64 0
|
@var64 = global i64 0
|
||||||
|
|
||||||
define void @test_fptosi() {
|
define void @test_fptosi() {
|
||||||
; CHECK: test_fptosi:
|
; CHECK-LABEL: test_fptosi:
|
||||||
%val = load fp128* @lhs
|
%val = load fp128* @lhs
|
||||||
|
|
||||||
%val32 = fptosi fp128 %val to i32
|
%val32 = fptosi fp128 %val to i32
|
||||||
@ -74,7 +74,7 @@ define void @test_fptosi() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_fptoui() {
|
define void @test_fptoui() {
|
||||||
; CHECK: test_fptoui:
|
; CHECK-LABEL: test_fptoui:
|
||||||
%val = load fp128* @lhs
|
%val = load fp128* @lhs
|
||||||
|
|
||||||
%val32 = fptoui fp128 %val to i32
|
%val32 = fptoui fp128 %val to i32
|
||||||
@ -89,7 +89,7 @@ define void @test_fptoui() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_sitofp() {
|
define void @test_sitofp() {
|
||||||
; CHECK: test_sitofp:
|
; CHECK-LABEL: test_sitofp:
|
||||||
|
|
||||||
%src32 = load i32* @var32
|
%src32 = load i32* @var32
|
||||||
%val32 = sitofp i32 %src32 to fp128
|
%val32 = sitofp i32 %src32 to fp128
|
||||||
@ -105,7 +105,7 @@ define void @test_sitofp() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_uitofp() {
|
define void @test_uitofp() {
|
||||||
; CHECK: test_uitofp:
|
; CHECK-LABEL: test_uitofp:
|
||||||
|
|
||||||
%src32 = load i32* @var32
|
%src32 = load i32* @var32
|
||||||
%val32 = uitofp i32 %src32 to fp128
|
%val32 = uitofp i32 %src32 to fp128
|
||||||
@ -121,7 +121,7 @@ define void @test_uitofp() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i1 @test_setcc1() {
|
define i1 @test_setcc1() {
|
||||||
; CHECK: test_setcc1:
|
; CHECK-LABEL: test_setcc1:
|
||||||
|
|
||||||
%lhs = load fp128* @lhs
|
%lhs = load fp128* @lhs
|
||||||
%rhs = load fp128* @rhs
|
%rhs = load fp128* @rhs
|
||||||
@ -140,7 +140,7 @@ define i1 @test_setcc1() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i1 @test_setcc2() {
|
define i1 @test_setcc2() {
|
||||||
; CHECK: test_setcc2:
|
; CHECK-LABEL: test_setcc2:
|
||||||
|
|
||||||
%lhs = load fp128* @lhs
|
%lhs = load fp128* @lhs
|
||||||
%rhs = load fp128* @rhs
|
%rhs = load fp128* @rhs
|
||||||
@ -165,7 +165,7 @@ define i1 @test_setcc2() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_br_cc() {
|
define i32 @test_br_cc() {
|
||||||
; CHECK: test_br_cc:
|
; CHECK-LABEL: test_br_cc:
|
||||||
|
|
||||||
%lhs = load fp128* @lhs
|
%lhs = load fp128* @lhs
|
||||||
%rhs = load fp128* @rhs
|
%rhs = load fp128* @rhs
|
||||||
@ -202,7 +202,7 @@ iffalse:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
|
define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
|
||||||
; CHECK: test_select:
|
; CHECK-LABEL: test_select:
|
||||||
|
|
||||||
%val = select i1 %cond, fp128 %lhs, fp128 %rhs
|
%val = select i1 %cond, fp128 %lhs, fp128 %rhs
|
||||||
store fp128 %val, fp128* @lhs
|
store fp128 %val, fp128* @lhs
|
||||||
@ -222,7 +222,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
|
|||||||
@vardouble = global double 0.0
|
@vardouble = global double 0.0
|
||||||
|
|
||||||
define void @test_round() {
|
define void @test_round() {
|
||||||
; CHECK: test_round:
|
; CHECK-LABEL: test_round:
|
||||||
|
|
||||||
%val = load fp128* @lhs
|
%val = load fp128* @lhs
|
||||||
|
|
||||||
@ -240,7 +240,7 @@ define void @test_round() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_extend() {
|
define void @test_extend() {
|
||||||
; CHECK: test_extend:
|
; CHECK-LABEL: test_extend:
|
||||||
|
|
||||||
%val = load fp128* @lhs
|
%val = load fp128* @lhs
|
||||||
|
|
||||||
@ -265,7 +265,7 @@ define fp128 @test_neg(fp128 %in) {
|
|||||||
; Make sure the weird hex constant below *is* -0.0
|
; Make sure the weird hex constant below *is* -0.0
|
||||||
; CHECK-NEXT: fp128 -0
|
; CHECK-NEXT: fp128 -0
|
||||||
|
|
||||||
; CHECK: test_neg:
|
; CHECK-LABEL: test_neg:
|
||||||
|
|
||||||
; Could in principle be optimized to fneg which we can't select, this makes
|
; Could in principle be optimized to fneg which we can't select, this makes
|
||||||
; sure that doesn't happen.
|
; sure that doesn't happen.
|
||||||
|
|||||||
@ -186,7 +186,7 @@ define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
|
|||||||
declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
|
declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
|
||||||
|
|
||||||
define i32 @test_extern() {
|
define i32 @test_extern() {
|
||||||
; CHECK: test_extern:
|
; CHECK-LABEL: test_extern:
|
||||||
call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0)
|
call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0)
|
||||||
; CHECK: bl memcpy
|
; CHECK: bl memcpy
|
||||||
ret i32 0
|
ret i32 0
|
||||||
|
|||||||
@ -5,7 +5,7 @@
|
|||||||
@var32_align64 = global [3 x i32] zeroinitializer, align 8
|
@var32_align64 = global [3 x i32] zeroinitializer, align 8
|
||||||
|
|
||||||
define i64 @test_align32() {
|
define i64 @test_align32() {
|
||||||
; CHECK: test_align32:
|
; CHECK-LABEL: test_align32:
|
||||||
%addr = bitcast [3 x i32]* @var32 to i64*
|
%addr = bitcast [3 x i32]* @var32 to i64*
|
||||||
|
|
||||||
; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
|
; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
|
||||||
@ -19,7 +19,7 @@ define i64 @test_align32() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_align64() {
|
define i64 @test_align64() {
|
||||||
; CHECK: test_align64:
|
; CHECK-LABEL: test_align64:
|
||||||
%addr = bitcast [3 x i64]* @var64 to i64*
|
%addr = bitcast [3 x i64]* @var64 to i64*
|
||||||
|
|
||||||
; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be
|
; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be
|
||||||
@ -33,7 +33,7 @@ define i64 @test_align64() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_var32_align64() {
|
define i64 @test_var32_align64() {
|
||||||
; CHECK: test_var32_align64:
|
; CHECK-LABEL: test_var32_align64:
|
||||||
%addr = bitcast [3 x i32]* @var32_align64 to i64*
|
%addr = bitcast [3 x i32]* @var32_align64 to i64*
|
||||||
|
|
||||||
; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
|
; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
|
||||||
@ -49,7 +49,7 @@ define i64 @test_var32_align64() {
|
|||||||
@yet_another_var = external global {i32, i32}
|
@yet_another_var = external global {i32, i32}
|
||||||
|
|
||||||
define i64 @test_yet_another_var() {
|
define i64 @test_yet_another_var() {
|
||||||
; CHECK: test_yet_another_var:
|
; CHECK-LABEL: test_yet_another_var:
|
||||||
|
|
||||||
; @yet_another_var has a preferred alignment of 8, but that's not enough if
|
; @yet_another_var has a preferred alignment of 8, but that's not enough if
|
||||||
; we're going to be linking against other things. Its ABI alignment is only 4
|
; we're going to be linking against other things. Its ABI alignment is only 4
|
||||||
@ -62,7 +62,7 @@ define i64 @test_yet_another_var() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64()* @test_functions() {
|
define i64()* @test_functions() {
|
||||||
; CHECK: test_functions:
|
; CHECK-LABEL: test_functions:
|
||||||
ret i64()* @test_yet_another_var
|
ret i64()* @test_yet_another_var
|
||||||
; CHECK: adrp [[HIBITS:x[0-9]+]], test_yet_another_var
|
; CHECK: adrp [[HIBITS:x[0-9]+]], test_yet_another_var
|
||||||
; CHECK: add x0, [[HIBITS]], #:lo12:test_yet_another_var
|
; CHECK: add x0, [[HIBITS]], #:lo12:test_yet_another_var
|
||||||
|
|||||||
@ -26,4 +26,4 @@ define i64 @check_field() {
|
|||||||
%diff = sub i64 %endi, %starti
|
%diff = sub i64 %endi, %starti
|
||||||
ret i64 %diff
|
ret i64 %diff
|
||||||
; CHECK: movz x0, #16
|
; CHECK: movz x0, #16
|
||||||
}
|
}
|
||||||
|
|||||||
@ -6,4 +6,4 @@ define internal void @_GLOBAL__I_a() section ".text.startup" {
|
|||||||
|
|
||||||
@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
|
@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
|
||||||
|
|
||||||
; CHECK: .section .init_array
|
; CHECK: .section .init_array
|
||||||
|
|||||||
@ -4,4 +4,4 @@ define void @foo() {
|
|||||||
; Out of range immediate for I.
|
; Out of range immediate for I.
|
||||||
call void asm sideeffect "add x0, x0, $0", "I"(i32 4096)
|
call void asm sideeffect "add x0, x0, $0", "I"(i32 4096)
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -4,4 +4,4 @@ define void @foo() {
|
|||||||
; 32-bit bitpattern ending in 1101 can't be produced.
|
; 32-bit bitpattern ending in 1101 can't be produced.
|
||||||
call void asm sideeffect "and w0, w0, $0", "K"(i32 13)
|
call void asm sideeffect "and w0, w0, $0", "K"(i32 13)
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -4,4 +4,4 @@ define void @foo() {
|
|||||||
; 32-bit bitpattern ending in 1101 can't be produced.
|
; 32-bit bitpattern ending in 1101 can't be produced.
|
||||||
call void asm sideeffect "and w0, w0, $0", "K"(i64 4294967296)
|
call void asm sideeffect "and w0, w0, $0", "K"(i64 4294967296)
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -4,4 +4,4 @@ define void @foo() {
|
|||||||
; 32-bit bitpattern ending in 1101 can't be produced.
|
; 32-bit bitpattern ending in 1101 can't be produced.
|
||||||
call void asm sideeffect "and x0, x0, $0", "L"(i32 13)
|
call void asm sideeffect "and x0, x0, $0", "L"(i32 13)
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -1,21 +1,21 @@
|
|||||||
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
|
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
|
||||||
|
|
||||||
define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
|
define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
|
||||||
; CHECK: test_inline_constraint_r:
|
; CHECK-LABEL: test_inline_constraint_r:
|
||||||
%val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset)
|
%val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset)
|
||||||
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
|
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
|
||||||
ret i64 %val
|
ret i64 %val
|
||||||
}
|
}
|
||||||
|
|
||||||
define i16 @test_small_reg(i16 %lhs, i16 %rhs) {
|
define i16 @test_small_reg(i16 %lhs, i16 %rhs) {
|
||||||
; CHECK: test_small_reg:
|
; CHECK-LABEL: test_small_reg:
|
||||||
%val = call i16 asm sideeffect "add $0, $1, $2, sxth", "=r,r,r"(i16 %lhs, i16 %rhs)
|
%val = call i16 asm sideeffect "add $0, $1, $2, sxth", "=r,r,r"(i16 %lhs, i16 %rhs)
|
||||||
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
|
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
|
||||||
ret i16 %val
|
ret i16 %val
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
|
define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
|
||||||
; CHECK: test_inline_constraint_r_imm:
|
; CHECK-LABEL: test_inline_constraint_r_imm:
|
||||||
%val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 4, i32 12)
|
%val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 4, i32 12)
|
||||||
; CHECK: movz [[FOUR:x[0-9]+]], #4
|
; CHECK: movz [[FOUR:x[0-9]+]], #4
|
||||||
; CHECK: movz [[TWELVE:w[0-9]+]], #12
|
; CHECK: movz [[TWELVE:w[0-9]+]], #12
|
||||||
@ -26,7 +26,7 @@ define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
|
|||||||
; m is permitted to have a base/offset form. We don't do that
|
; m is permitted to have a base/offset form. We don't do that
|
||||||
; currently though.
|
; currently though.
|
||||||
define i32 @test_inline_constraint_m(i32 *%ptr) {
|
define i32 @test_inline_constraint_m(i32 *%ptr) {
|
||||||
; CHECK: test_inline_constraint_m:
|
; CHECK-LABEL: test_inline_constraint_m:
|
||||||
%val = call i32 asm "ldr $0, $1", "=r,m"(i32 *%ptr)
|
%val = call i32 asm "ldr $0, $1", "=r,m"(i32 *%ptr)
|
||||||
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
|
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
|
||||||
ret i32 %val
|
ret i32 %val
|
||||||
@ -36,7 +36,7 @@ define i32 @test_inline_constraint_m(i32 *%ptr) {
|
|||||||
|
|
||||||
; Q should *never* have base/offset form even if given the chance.
|
; Q should *never* have base/offset form even if given the chance.
|
||||||
define i32 @test_inline_constraint_Q(i32 *%ptr) {
|
define i32 @test_inline_constraint_Q(i32 *%ptr) {
|
||||||
; CHECK: test_inline_constraint_Q:
|
; CHECK-LABEL: test_inline_constraint_Q:
|
||||||
%val = call i32 asm "ldr $0, $1", "=r,Q"(i32* getelementptr([8 x i32]* @arr, i32 0, i32 1))
|
%val = call i32 asm "ldr $0, $1", "=r,Q"(i32* getelementptr([8 x i32]* @arr, i32 0, i32 1))
|
||||||
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
|
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
|
||||||
ret i32 %val
|
ret i32 %val
|
||||||
@ -45,7 +45,7 @@ define i32 @test_inline_constraint_Q(i32 *%ptr) {
|
|||||||
@dump = global fp128 zeroinitializer
|
@dump = global fp128 zeroinitializer
|
||||||
|
|
||||||
define void @test_inline_constraint_I() {
|
define void @test_inline_constraint_I() {
|
||||||
; CHECK: test_inline_constraint_I:
|
; CHECK-LABEL: test_inline_constraint_I:
|
||||||
call void asm sideeffect "add x0, x0, $0", "I"(i32 0)
|
call void asm sideeffect "add x0, x0, $0", "I"(i32 0)
|
||||||
call void asm sideeffect "add x0, x0, $0", "I"(i64 4095)
|
call void asm sideeffect "add x0, x0, $0", "I"(i64 4095)
|
||||||
; CHECK: add x0, x0, #0
|
; CHECK: add x0, x0, #0
|
||||||
@ -57,7 +57,7 @@ define void @test_inline_constraint_I() {
|
|||||||
; Skip J because it's useless
|
; Skip J because it's useless
|
||||||
|
|
||||||
define void @test_inline_constraint_K() {
|
define void @test_inline_constraint_K() {
|
||||||
; CHECK: test_inline_constraint_K:
|
; CHECK-LABEL: test_inline_constraint_K:
|
||||||
call void asm sideeffect "and w0, w0, $0", "K"(i32 2863311530) ; = 0xaaaaaaaa
|
call void asm sideeffect "and w0, w0, $0", "K"(i32 2863311530) ; = 0xaaaaaaaa
|
||||||
call void asm sideeffect "and w0, w0, $0", "K"(i32 65535)
|
call void asm sideeffect "and w0, w0, $0", "K"(i32 65535)
|
||||||
; CHECK: and w0, w0, #-1431655766
|
; CHECK: and w0, w0, #-1431655766
|
||||||
@ -67,7 +67,7 @@ define void @test_inline_constraint_K() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_inline_constraint_L() {
|
define void @test_inline_constraint_L() {
|
||||||
; CHECK: test_inline_constraint_L:
|
; CHECK-LABEL: test_inline_constraint_L:
|
||||||
call void asm sideeffect "and x0, x0, $0", "L"(i64 4294967296) ; = 0xaaaaaaaa
|
call void asm sideeffect "and x0, x0, $0", "L"(i64 4294967296) ; = 0xaaaaaaaa
|
||||||
call void asm sideeffect "and x0, x0, $0", "L"(i64 65535)
|
call void asm sideeffect "and x0, x0, $0", "L"(i64 65535)
|
||||||
; CHECK: and x0, x0, #4294967296
|
; CHECK: and x0, x0, #4294967296
|
||||||
@ -81,7 +81,7 @@ define void @test_inline_constraint_L() {
|
|||||||
@var = global i32 0
|
@var = global i32 0
|
||||||
|
|
||||||
define void @test_inline_constraint_S() {
|
define void @test_inline_constraint_S() {
|
||||||
; CHECK: test_inline_constraint_S:
|
; CHECK-LABEL: test_inline_constraint_S:
|
||||||
call void asm sideeffect "adrp x0, $0", "S"(i32* @var)
|
call void asm sideeffect "adrp x0, $0", "S"(i32* @var)
|
||||||
call void asm sideeffect "adrp x0, ${0:A}", "S"(i32* @var)
|
call void asm sideeffect "adrp x0, ${0:A}", "S"(i32* @var)
|
||||||
call void asm sideeffect "add x0, x0, ${0:L}", "S"(i32* @var)
|
call void asm sideeffect "add x0, x0, ${0:L}", "S"(i32* @var)
|
||||||
@ -92,7 +92,7 @@ define void @test_inline_constraint_S() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_inline_constraint_S_label(i1 %in) {
|
define i32 @test_inline_constraint_S_label(i1 %in) {
|
||||||
; CHECK: test_inline_constraint_S_label:
|
; CHECK-LABEL: test_inline_constraint_S_label:
|
||||||
call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc))
|
call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc))
|
||||||
; CHECK: adr x0, .Ltmp{{[0-9]+}}
|
; CHECK: adr x0, .Ltmp{{[0-9]+}}
|
||||||
br i1 %in, label %loc, label %loc2
|
br i1 %in, label %loc, label %loc2
|
||||||
@ -103,15 +103,15 @@ loc2:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_inline_constraint_Y() {
|
define void @test_inline_constraint_Y() {
|
||||||
; CHECK: test_inline_constraint_Y:
|
; CHECK-LABEL: test_inline_constraint_Y:
|
||||||
call void asm sideeffect "fcmp s0, $0", "Y"(float 0.0)
|
call void asm sideeffect "fcmp s0, $0", "Y"(float 0.0)
|
||||||
; CHECK: fcmp s0, #0.0
|
; CHECK: fcmp s0, #0.0
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
define void @test_inline_constraint_Z() {
|
define void @test_inline_constraint_Z() {
|
||||||
; CHECK: test_inline_constraint_Z:
|
; CHECK-LABEL: test_inline_constraint_Z:
|
||||||
call void asm sideeffect "cmp w0, $0", "Z"(i32 0)
|
call void asm sideeffect "cmp w0, $0", "Z"(i32 0)
|
||||||
; CHECK: cmp w0, #0
|
; CHECK: cmp w0, #0
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -9,7 +9,7 @@
|
|||||||
@var_tlsle = thread_local(localexec) global i32 0
|
@var_tlsle = thread_local(localexec) global i32 0
|
||||||
|
|
||||||
define void @test_inline_modifier_L() nounwind {
|
define void @test_inline_modifier_L() nounwind {
|
||||||
; CHECK: test_inline_modifier_L:
|
; CHECK-LABEL: test_inline_modifier_L:
|
||||||
call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_simple)
|
call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_simple)
|
||||||
call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_got)
|
call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_got)
|
||||||
call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_tlsgd)
|
call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_tlsgd)
|
||||||
@ -34,7 +34,7 @@ define void @test_inline_modifier_L() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_inline_modifier_G() nounwind {
|
define void @test_inline_modifier_G() nounwind {
|
||||||
; CHECK: test_inline_modifier_G:
|
; CHECK-LABEL: test_inline_modifier_G:
|
||||||
call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsld)
|
call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsld)
|
||||||
call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsle)
|
call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsle)
|
||||||
; CHECK: add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12
|
; CHECK: add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12
|
||||||
@ -47,7 +47,7 @@ define void @test_inline_modifier_G() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_inline_modifier_A() nounwind {
|
define void @test_inline_modifier_A() nounwind {
|
||||||
; CHECK: test_inline_modifier_A:
|
; CHECK-LABEL: test_inline_modifier_A:
|
||||||
call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_simple)
|
call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_simple)
|
||||||
call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_got)
|
call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_got)
|
||||||
call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_tlsgd)
|
call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_tlsgd)
|
||||||
@ -67,7 +67,7 @@ define void @test_inline_modifier_A() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind {
|
define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind {
|
||||||
; CHECK: test_inline_modifier_wx:
|
; CHECK-LABEL: test_inline_modifier_wx:
|
||||||
call i32 asm sideeffect "add $0, $0, $0", "=r,0"(i32 %small)
|
call i32 asm sideeffect "add $0, $0, $0", "=r,0"(i32 %small)
|
||||||
call i32 asm sideeffect "add ${0:w}, ${0:w}, ${0:w}", "=r,0"(i32 %small)
|
call i32 asm sideeffect "add ${0:w}, ${0:w}, ${0:w}", "=r,0"(i32 %small)
|
||||||
call i32 asm sideeffect "add ${0:x}, ${0:x}, ${0:x}", "=r,0"(i32 %small)
|
call i32 asm sideeffect "add ${0:x}, ${0:x}, ${0:x}", "=r,0"(i32 %small)
|
||||||
@ -91,7 +91,7 @@ define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_inline_modifier_bhsdq() nounwind {
|
define void @test_inline_modifier_bhsdq() nounwind {
|
||||||
; CHECK: test_inline_modifier_bhsdq:
|
; CHECK-LABEL: test_inline_modifier_bhsdq:
|
||||||
call float asm sideeffect "ldr ${0:b}, [sp]", "=w"()
|
call float asm sideeffect "ldr ${0:b}, [sp]", "=w"()
|
||||||
call float asm sideeffect "ldr ${0:h}, [sp]", "=w"()
|
call float asm sideeffect "ldr ${0:h}, [sp]", "=w"()
|
||||||
call float asm sideeffect "ldr ${0:s}, [sp]", "=w"()
|
call float asm sideeffect "ldr ${0:s}, [sp]", "=w"()
|
||||||
@ -117,9 +117,9 @@ define void @test_inline_modifier_bhsdq() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_inline_modifier_c() nounwind {
|
define void @test_inline_modifier_c() nounwind {
|
||||||
; CHECK: test_inline_modifier_c:
|
; CHECK-LABEL: test_inline_modifier_c:
|
||||||
call void asm sideeffect "adr x0, ${0:c}", "i"(i32 3)
|
call void asm sideeffect "adr x0, ${0:c}", "i"(i32 3)
|
||||||
; CHECK: adr x0, 3
|
; CHECK: adr x0, 3
|
||||||
|
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -4,7 +4,7 @@ declare void @use_addr(i8*)
|
|||||||
@addr = global i8* null
|
@addr = global i8* null
|
||||||
|
|
||||||
define void @test_bigframe() {
|
define void @test_bigframe() {
|
||||||
; CHECK: test_bigframe:
|
; CHECK-LABEL: test_bigframe:
|
||||||
; CHECK: .cfi_startproc
|
; CHECK: .cfi_startproc
|
||||||
|
|
||||||
%var1 = alloca i8, i32 20000000
|
%var1 = alloca i8, i32 20000000
|
||||||
@ -50,7 +50,7 @@ define void @test_bigframe() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_mediumframe() {
|
define void @test_mediumframe() {
|
||||||
; CHECK: test_mediumframe:
|
; CHECK-LABEL: test_mediumframe:
|
||||||
%var1 = alloca i8, i32 1000000
|
%var1 = alloca i8, i32 1000000
|
||||||
%var2 = alloca i8, i32 16
|
%var2 = alloca i8, i32 16
|
||||||
%var3 = alloca i8, i32 1000000
|
%var3 = alloca i8, i32 1000000
|
||||||
@ -93,7 +93,7 @@ define void @test_mediumframe() {
|
|||||||
; If temporary registers are allocated for adjustment, they should *not* clobber
|
; If temporary registers are allocated for adjustment, they should *not* clobber
|
||||||
; argument registers.
|
; argument registers.
|
||||||
define void @test_tempallocation([8 x i64] %val) nounwind {
|
define void @test_tempallocation([8 x i64] %val) nounwind {
|
||||||
; CHECK: test_tempallocation:
|
; CHECK-LABEL: test_tempallocation:
|
||||||
%var = alloca i8, i32 1000000
|
%var = alloca i8, i32 1000000
|
||||||
; CHECK: sub sp, sp,
|
; CHECK: sub sp, sp,
|
||||||
|
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@var64 = global i64 0
|
@var64 = global i64 0
|
||||||
|
|
||||||
define void @test_and(i32 %in32, i64 %in64) {
|
define void @test_and(i32 %in32, i64 %in64) {
|
||||||
; CHECK: test_and:
|
; CHECK-LABEL: test_and:
|
||||||
|
|
||||||
%val0 = and i32 %in32, 2863311530
|
%val0 = and i32 %in32, 2863311530
|
||||||
store volatile i32 %val0, i32* @var32
|
store volatile i32 %val0, i32* @var32
|
||||||
@ -26,7 +26,7 @@ define void @test_and(i32 %in32, i64 %in64) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_orr(i32 %in32, i64 %in64) {
|
define void @test_orr(i32 %in32, i64 %in64) {
|
||||||
; CHECK: test_orr:
|
; CHECK-LABEL: test_orr:
|
||||||
|
|
||||||
%val0 = or i32 %in32, 2863311530
|
%val0 = or i32 %in32, 2863311530
|
||||||
store volatile i32 %val0, i32* @var32
|
store volatile i32 %val0, i32* @var32
|
||||||
@ -48,7 +48,7 @@ define void @test_orr(i32 %in32, i64 %in64) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_eor(i32 %in32, i64 %in64) {
|
define void @test_eor(i32 %in32, i64 %in64) {
|
||||||
; CHECK: test_eor:
|
; CHECK-LABEL: test_eor:
|
||||||
|
|
||||||
%val0 = xor i32 %in32, 2863311530
|
%val0 = xor i32 %in32, 2863311530
|
||||||
store volatile i32 %val0, i32* @var32
|
store volatile i32 %val0, i32* @var32
|
||||||
@ -70,7 +70,7 @@ define void @test_eor(i32 %in32, i64 %in64) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_mov(i32 %in32, i64 %in64) {
|
define void @test_mov(i32 %in32, i64 %in64) {
|
||||||
; CHECK: test_mov:
|
; CHECK-LABEL: test_mov:
|
||||||
%val0 = add i32 %in32, 2863311530
|
%val0 = add i32 %in32, 2863311530
|
||||||
store i32 %val0, i32* @var32
|
store i32 %val0, i32* @var32
|
||||||
; CHECK: orr {{w[0-9]+}}, wzr, #0xaaaaaaaa
|
; CHECK: orr {{w[0-9]+}}, wzr, #0xaaaaaaaa
|
||||||
|
|||||||
@ -1,50 +1,50 @@
|
|||||||
; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
|
||||||
|
|
||||||
define i64 @test0() {
|
define i64 @test0() {
|
||||||
; CHECK: test0:
|
; CHECK-LABEL: test0:
|
||||||
; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
|
; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
|
||||||
; CHECK: mov x0, xzr
|
; CHECK: mov x0, xzr
|
||||||
ret i64 0
|
ret i64 0
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test1() {
|
define i64 @test1() {
|
||||||
; CHECK: test1:
|
; CHECK-LABEL: test1:
|
||||||
; CHECK: movz x0, #1
|
; CHECK: movz x0, #1
|
||||||
ret i64 1
|
ret i64 1
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test2() {
|
define i64 @test2() {
|
||||||
; CHECK: test2:
|
; CHECK-LABEL: test2:
|
||||||
; CHECK: movz x0, #65535
|
; CHECK: movz x0, #65535
|
||||||
ret i64 65535
|
ret i64 65535
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test3() {
|
define i64 @test3() {
|
||||||
; CHECK: test3:
|
; CHECK-LABEL: test3:
|
||||||
; CHECK: movz x0, #1, lsl #16
|
; CHECK: movz x0, #1, lsl #16
|
||||||
ret i64 65536
|
ret i64 65536
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test4() {
|
define i64 @test4() {
|
||||||
; CHECK: test4:
|
; CHECK-LABEL: test4:
|
||||||
; CHECK: movz x0, #65535, lsl #16
|
; CHECK: movz x0, #65535, lsl #16
|
||||||
ret i64 4294901760
|
ret i64 4294901760
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test5() {
|
define i64 @test5() {
|
||||||
; CHECK: test5:
|
; CHECK-LABEL: test5:
|
||||||
; CHECK: movz x0, #1, lsl #32
|
; CHECK: movz x0, #1, lsl #32
|
||||||
ret i64 4294967296
|
ret i64 4294967296
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test6() {
|
define i64 @test6() {
|
||||||
; CHECK: test6:
|
; CHECK-LABEL: test6:
|
||||||
; CHECK: movz x0, #65535, lsl #32
|
; CHECK: movz x0, #65535, lsl #32
|
||||||
ret i64 281470681743360
|
ret i64 281470681743360
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test7() {
|
define i64 @test7() {
|
||||||
; CHECK: test7:
|
; CHECK-LABEL: test7:
|
||||||
; CHECK: movz x0, #1, lsl #48
|
; CHECK: movz x0, #1, lsl #48
|
||||||
ret i64 281474976710656
|
ret i64 281474976710656
|
||||||
}
|
}
|
||||||
@ -52,19 +52,19 @@ define i64 @test7() {
|
|||||||
; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
|
; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
|
||||||
; couldn't. Useful even for i64
|
; couldn't. Useful even for i64
|
||||||
define i64 @test8() {
|
define i64 @test8() {
|
||||||
; CHECK: test8:
|
; CHECK-LABEL: test8:
|
||||||
; CHECK: movn w0, #60875
|
; CHECK: movn w0, #60875
|
||||||
ret i64 4294906420
|
ret i64 4294906420
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test9() {
|
define i64 @test9() {
|
||||||
; CHECK: test9:
|
; CHECK-LABEL: test9:
|
||||||
; CHECK: movn x0, #0
|
; CHECK: movn x0, #0
|
||||||
ret i64 -1
|
ret i64 -1
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test10() {
|
define i64 @test10() {
|
||||||
; CHECK: test10:
|
; CHECK-LABEL: test10:
|
||||||
; CHECK: movn x0, #60875, lsl #16
|
; CHECK: movn x0, #60875, lsl #16
|
||||||
ret i64 18446744069720047615
|
ret i64 18446744069720047615
|
||||||
}
|
}
|
||||||
@ -74,49 +74,49 @@ define i64 @test10() {
|
|||||||
@var32 = global i32 0
|
@var32 = global i32 0
|
||||||
|
|
||||||
define void @test11() {
|
define void @test11() {
|
||||||
; CHECK: test11:
|
; CHECK-LABEL: test11:
|
||||||
; CHECK: mov {{w[0-9]+}}, wzr
|
; CHECK: mov {{w[0-9]+}}, wzr
|
||||||
store i32 0, i32* @var32
|
store i32 0, i32* @var32
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
define void @test12() {
|
define void @test12() {
|
||||||
; CHECK: test12:
|
; CHECK-LABEL: test12:
|
||||||
; CHECK: movz {{w[0-9]+}}, #1
|
; CHECK: movz {{w[0-9]+}}, #1
|
||||||
store i32 1, i32* @var32
|
store i32 1, i32* @var32
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
define void @test13() {
|
define void @test13() {
|
||||||
; CHECK: test13:
|
; CHECK-LABEL: test13:
|
||||||
; CHECK: movz {{w[0-9]+}}, #65535
|
; CHECK: movz {{w[0-9]+}}, #65535
|
||||||
store i32 65535, i32* @var32
|
store i32 65535, i32* @var32
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
define void @test14() {
|
define void @test14() {
|
||||||
; CHECK: test14:
|
; CHECK-LABEL: test14:
|
||||||
; CHECK: movz {{w[0-9]+}}, #1, lsl #16
|
; CHECK: movz {{w[0-9]+}}, #1, lsl #16
|
||||||
store i32 65536, i32* @var32
|
store i32 65536, i32* @var32
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
define void @test15() {
|
define void @test15() {
|
||||||
; CHECK: test15:
|
; CHECK-LABEL: test15:
|
||||||
; CHECK: movz {{w[0-9]+}}, #65535, lsl #16
|
; CHECK: movz {{w[0-9]+}}, #65535, lsl #16
|
||||||
store i32 4294901760, i32* @var32
|
store i32 4294901760, i32* @var32
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
define void @test16() {
|
define void @test16() {
|
||||||
; CHECK: test16:
|
; CHECK-LABEL: test16:
|
||||||
; CHECK: movn {{w[0-9]+}}, #0
|
; CHECK: movn {{w[0-9]+}}, #0
|
||||||
store i32 -1, i32* @var32
|
store i32 -1, i32* @var32
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test17() {
|
define i64 @test17() {
|
||||||
; CHECK: test17:
|
; CHECK-LABEL: test17:
|
||||||
|
|
||||||
; Mustn't MOVN w0 here.
|
; Mustn't MOVN w0 here.
|
||||||
; CHECK: movn x0, #2
|
; CHECK: movn x0, #2
|
||||||
|
|||||||
@ -57,4 +57,4 @@ declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
|
|||||||
|
|
||||||
declare i8* @__cxa_begin_catch(i8*)
|
declare i8* @__cxa_begin_catch(i8*)
|
||||||
|
|
||||||
declare void @__cxa_end_catch()
|
declare void @__cxa_end_catch()
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
; actually capable of that (the test was omitted from LowerFormalArguments).
|
; actually capable of that (the test was omitted from LowerFormalArguments).
|
||||||
|
|
||||||
define void @test_bitcast_lower(<2 x i32> %a) {
|
define void @test_bitcast_lower(<2 x i32> %a) {
|
||||||
; CHECK: test_bitcast_lower:
|
; CHECK-LABEL: test_bitcast_lower:
|
||||||
|
|
||||||
ret void
|
ret void
|
||||||
; CHECK: ret
|
; CHECK: ret
|
||||||
|
|||||||
@ -16,4 +16,4 @@ define void @foo() {
|
|||||||
tail call void %func()
|
tail call void %func()
|
||||||
; CHECK: br {{x([0-79]|1[0-8])}}
|
; CHECK: br {{x([0-79]|1[0-8])}}
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -12,7 +12,7 @@
|
|||||||
declare void @bar(i8*)
|
declare void @bar(i8*)
|
||||||
|
|
||||||
define i64 @test_chains() {
|
define i64 @test_chains() {
|
||||||
; CHECK: test_chains:
|
; CHECK-LABEL: test_chains:
|
||||||
|
|
||||||
%locvar = alloca i8
|
%locvar = alloca i8
|
||||||
|
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
declare void @bar()
|
declare void @bar()
|
||||||
|
|
||||||
define void @test_w29_reserved() {
|
define void @test_w29_reserved() {
|
||||||
; CHECK: test_w29_reserved:
|
; CHECK-LABEL: test_w29_reserved:
|
||||||
; CHECK: .cfi_startproc
|
; CHECK: .cfi_startproc
|
||||||
; CHECK: .cfi_def_cfa sp, 96
|
; CHECK: .cfi_def_cfa sp, 96
|
||||||
; CHECK: add x29, sp, #{{[0-9]+}}
|
; CHECK: add x29, sp, #{{[0-9]+}}
|
||||||
|
|||||||
@ -12,11 +12,11 @@
|
|||||||
declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64)
|
declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64)
|
||||||
|
|
||||||
define i64 @test_select(i64 %lhs, i64 %rhs) {
|
define i64 @test_select(i64 %lhs, i64 %rhs) {
|
||||||
; CHECK: test_select:
|
; CHECK-LABEL: test_select:
|
||||||
|
|
||||||
%res = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %lhs, i64 %rhs)
|
%res = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %lhs, i64 %rhs)
|
||||||
%flag = extractvalue {i64, i1} %res, 1
|
%flag = extractvalue {i64, i1} %res, 1
|
||||||
%retval = select i1 %flag, i64 %lhs, i64 %rhs
|
%retval = select i1 %flag, i64 %lhs, i64 %rhs
|
||||||
ret i64 %retval
|
ret i64 %retval
|
||||||
; CHECK: ret
|
; CHECK: ret
|
||||||
}
|
}
|
||||||
|
|||||||
@ -32,4 +32,4 @@ declare double @sin(double) readonly
|
|||||||
declare fp128 @sinl(fp128) readonly
|
declare fp128 @sinl(fp128) readonly
|
||||||
declare float @cosf(float) readonly
|
declare float @cosf(float) readonly
|
||||||
declare double @cos(double) readonly
|
declare double @cos(double) readonly
|
||||||
declare fp128 @cosl(fp128) readonly
|
declare fp128 @cosl(fp128) readonly
|
||||||
|
|||||||
@ -8,7 +8,7 @@
|
|||||||
@general_dynamic_var = external thread_local global i32
|
@general_dynamic_var = external thread_local global i32
|
||||||
|
|
||||||
define i32 @test_generaldynamic() {
|
define i32 @test_generaldynamic() {
|
||||||
; CHECK: test_generaldynamic:
|
; CHECK-LABEL: test_generaldynamic:
|
||||||
|
|
||||||
%val = load i32* @general_dynamic_var
|
%val = load i32* @general_dynamic_var
|
||||||
ret i32 %val
|
ret i32 %val
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@general_dynamic_var = external thread_local global i32
|
@general_dynamic_var = external thread_local global i32
|
||||||
|
|
||||||
define i32 @test_generaldynamic() {
|
define i32 @test_generaldynamic() {
|
||||||
; CHECK: test_generaldynamic:
|
; CHECK-LABEL: test_generaldynamic:
|
||||||
|
|
||||||
%val = load i32* @general_dynamic_var
|
%val = load i32* @general_dynamic_var
|
||||||
ret i32 %val
|
ret i32 %val
|
||||||
@ -26,7 +26,7 @@ define i32 @test_generaldynamic() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32* @test_generaldynamic_addr() {
|
define i32* @test_generaldynamic_addr() {
|
||||||
; CHECK: test_generaldynamic_addr:
|
; CHECK-LABEL: test_generaldynamic_addr:
|
||||||
|
|
||||||
ret i32* @general_dynamic_var
|
ret i32* @general_dynamic_var
|
||||||
|
|
||||||
@ -49,7 +49,7 @@ define i32* @test_generaldynamic_addr() {
|
|||||||
@local_dynamic_var = external thread_local(localdynamic) global i32
|
@local_dynamic_var = external thread_local(localdynamic) global i32
|
||||||
|
|
||||||
define i32 @test_localdynamic() {
|
define i32 @test_localdynamic() {
|
||||||
; CHECK: test_localdynamic:
|
; CHECK-LABEL: test_localdynamic:
|
||||||
|
|
||||||
%val = load i32* @local_dynamic_var
|
%val = load i32* @local_dynamic_var
|
||||||
ret i32 %val
|
ret i32 %val
|
||||||
@ -73,7 +73,7 @@ define i32 @test_localdynamic() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32* @test_localdynamic_addr() {
|
define i32* @test_localdynamic_addr() {
|
||||||
; CHECK: test_localdynamic_addr:
|
; CHECK-LABEL: test_localdynamic_addr:
|
||||||
|
|
||||||
ret i32* @local_dynamic_var
|
ret i32* @local_dynamic_var
|
||||||
|
|
||||||
@ -101,7 +101,7 @@ define i32* @test_localdynamic_addr() {
|
|||||||
@local_dynamic_var2 = external thread_local(localdynamic) global i32
|
@local_dynamic_var2 = external thread_local(localdynamic) global i32
|
||||||
|
|
||||||
define i32 @test_localdynamic_deduplicate() {
|
define i32 @test_localdynamic_deduplicate() {
|
||||||
; CHECK: test_localdynamic_deduplicate:
|
; CHECK-LABEL: test_localdynamic_deduplicate:
|
||||||
|
|
||||||
%val = load i32* @local_dynamic_var
|
%val = load i32* @local_dynamic_var
|
||||||
%val2 = load i32* @local_dynamic_var2
|
%val2 = load i32* @local_dynamic_var2
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@initial_exec_var = external thread_local(initialexec) global i32
|
@initial_exec_var = external thread_local(initialexec) global i32
|
||||||
|
|
||||||
define i32 @test_initial_exec() {
|
define i32 @test_initial_exec() {
|
||||||
; CHECK: test_initial_exec:
|
; CHECK-LABEL: test_initial_exec:
|
||||||
%val = load i32* @initial_exec_var
|
%val = load i32* @initial_exec_var
|
||||||
|
|
||||||
; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
|
; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
|
||||||
@ -19,7 +19,7 @@ define i32 @test_initial_exec() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32* @test_initial_exec_addr() {
|
define i32* @test_initial_exec_addr() {
|
||||||
; CHECK: test_initial_exec_addr:
|
; CHECK-LABEL: test_initial_exec_addr:
|
||||||
ret i32* @initial_exec_var
|
ret i32* @initial_exec_var
|
||||||
|
|
||||||
; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
|
; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
|
||||||
@ -35,7 +35,7 @@ define i32* @test_initial_exec_addr() {
|
|||||||
@local_exec_var = thread_local(initialexec) global i32 0
|
@local_exec_var = thread_local(initialexec) global i32 0
|
||||||
|
|
||||||
define i32 @test_local_exec() {
|
define i32 @test_local_exec() {
|
||||||
; CHECK: test_local_exec:
|
; CHECK-LABEL: test_local_exec:
|
||||||
%val = load i32* @local_exec_var
|
%val = load i32* @local_exec_var
|
||||||
|
|
||||||
; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
|
; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
|
||||||
@ -50,7 +50,7 @@ define i32 @test_local_exec() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32* @test_local_exec_addr() {
|
define i32* @test_local_exec_addr() {
|
||||||
; CHECK: test_local_exec_addr:
|
; CHECK-LABEL: test_local_exec_addr:
|
||||||
ret i32* @local_exec_var
|
ret i32* @local_exec_var
|
||||||
|
|
||||||
; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
|
; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
|
||||||
|
|||||||
@ -7,7 +7,7 @@
|
|||||||
@var64 = global i64 0
|
@var64 = global i64 0
|
||||||
|
|
||||||
define i32 @test_tbz() {
|
define i32 @test_tbz() {
|
||||||
; CHECK: test_tbz:
|
; CHECK-LABEL: test_tbz:
|
||||||
|
|
||||||
%val = load i32* @var32
|
%val = load i32* @var32
|
||||||
%val64 = load i64* @var64
|
%val64 = load i64* @var64
|
||||||
|
|||||||
@ -7,7 +7,7 @@
|
|||||||
declare void @llvm.va_start(i8*)
|
declare void @llvm.va_start(i8*)
|
||||||
|
|
||||||
define void @test_simple(i32 %n, ...) {
|
define void @test_simple(i32 %n, ...) {
|
||||||
; CHECK: test_simple:
|
; CHECK-LABEL: test_simple:
|
||||||
; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
|
; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
|
||||||
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
|
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
|
||||||
; CHECK: str q7, [x[[FPRBASE]], #112]
|
; CHECK: str q7, [x[[FPRBASE]], #112]
|
||||||
@ -37,7 +37,7 @@ define void @test_simple(i32 %n, ...) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
|
define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
|
||||||
; CHECK: test_fewargs:
|
; CHECK-LABEL: test_fewargs:
|
||||||
; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
|
; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
|
||||||
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
|
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
|
||||||
; CHECK: str q7, [x[[FPRBASE]], #96]
|
; CHECK: str q7, [x[[FPRBASE]], #96]
|
||||||
@ -67,7 +67,7 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_nospare([8 x i64], [8 x float], ...) {
|
define void @test_nospare([8 x i64], [8 x float], ...) {
|
||||||
; CHECK: test_nospare:
|
; CHECK-LABEL: test_nospare:
|
||||||
|
|
||||||
%addr = bitcast %va_list* @var to i8*
|
%addr = bitcast %va_list* @var to i8*
|
||||||
call void @llvm.va_start(i8* %addr)
|
call void @llvm.va_start(i8* %addr)
|
||||||
@ -81,7 +81,7 @@ define void @test_nospare([8 x i64], [8 x float], ...) {
|
|||||||
; If there are non-variadic arguments on the stack (here two i64s) then the
|
; If there are non-variadic arguments on the stack (here two i64s) then the
|
||||||
; __stack field should point just past them.
|
; __stack field should point just past them.
|
||||||
define void @test_offsetstack([10 x i64], [3 x float], ...) {
|
define void @test_offsetstack([10 x i64], [3 x float], ...) {
|
||||||
; CHECK: test_offsetstack:
|
; CHECK-LABEL: test_offsetstack:
|
||||||
; CHECK: sub sp, sp, #80
|
; CHECK: sub sp, sp, #80
|
||||||
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
|
; CHECK: mov x[[FPRBASE:[0-9]+]], sp
|
||||||
; CHECK: str q7, [x[[FPRBASE]], #64]
|
; CHECK: str q7, [x[[FPRBASE]], #64]
|
||||||
@ -108,7 +108,7 @@ define void @test_offsetstack([10 x i64], [3 x float], ...) {
|
|||||||
declare void @llvm.va_end(i8*)
|
declare void @llvm.va_end(i8*)
|
||||||
|
|
||||||
define void @test_va_end() nounwind {
|
define void @test_va_end() nounwind {
|
||||||
; CHECK: test_va_end:
|
; CHECK-LABEL: test_va_end:
|
||||||
; CHECK-NEXT: BB#0
|
; CHECK-NEXT: BB#0
|
||||||
|
|
||||||
%addr = bitcast %va_list* @var to i8*
|
%addr = bitcast %va_list* @var to i8*
|
||||||
@ -123,7 +123,7 @@ declare void @llvm.va_copy(i8* %dest, i8* %src)
|
|||||||
@second_list = global %va_list zeroinitializer
|
@second_list = global %va_list zeroinitializer
|
||||||
|
|
||||||
define void @test_va_copy() {
|
define void @test_va_copy() {
|
||||||
; CHECK: test_va_copy:
|
; CHECK-LABEL: test_va_copy:
|
||||||
%srcaddr = bitcast %va_list* @var to i8*
|
%srcaddr = bitcast %va_list* @var to i8*
|
||||||
%dstaddr = bitcast %va_list* @second_list to i8*
|
%dstaddr = bitcast %va_list* @second_list to i8*
|
||||||
call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
|
call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
@var64 = global i64 0
|
@var64 = global i64 0
|
||||||
|
|
||||||
define void @test_zr() {
|
define void @test_zr() {
|
||||||
; CHECK: test_zr:
|
; CHECK-LABEL: test_zr:
|
||||||
|
|
||||||
store i32 0, i32* @var32
|
store i32 0, i32* @var32
|
||||||
; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
|
; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
|
||||||
@ -16,7 +16,7 @@ define void @test_zr() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_sp(i32 %val) {
|
define void @test_sp(i32 %val) {
|
||||||
; CHECK: test_sp:
|
; CHECK-LABEL: test_sp:
|
||||||
|
|
||||||
; Important correctness point here is that LLVM doesn't try to use xzr
|
; Important correctness point here is that LLVM doesn't try to use xzr
|
||||||
; as an addressing register: "str w0, [xzr]" is not a valid A64
|
; as an addressing register: "str w0, [xzr]" is not a valid A64
|
||||||
@ -28,4 +28,4 @@ define void @test_sp(i32 %val) {
|
|||||||
|
|
||||||
ret void
|
ret void
|
||||||
; CHECK: ret
|
; CHECK: ret
|
||||||
}
|
}
|
||||||
|
|||||||
@ -15,7 +15,7 @@
|
|||||||
|
|
||||||
define i32 @test() nounwind optsize ssp {
|
define i32 @test() nounwind optsize ssp {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test:
|
; CHECK-LABEL: test:
|
||||||
; CHECK: push
|
; CHECK: push
|
||||||
; CHECK-NOT: push
|
; CHECK-NOT: push
|
||||||
%block_size = alloca i32, align 4
|
%block_size = alloca i32, align 4
|
||||||
|
|||||||
@ -6,7 +6,7 @@
|
|||||||
@i8_src2 = global <2 x i8> <i8 2, i8 1>
|
@i8_src2 = global <2 x i8> <i8 2, i8 1>
|
||||||
|
|
||||||
define void @test_neon_vector_add_2xi8() nounwind {
|
define void @test_neon_vector_add_2xi8() nounwind {
|
||||||
; CHECK: test_neon_vector_add_2xi8:
|
; CHECK-LABEL: test_neon_vector_add_2xi8:
|
||||||
%1 = load <2 x i8>* @i8_src1
|
%1 = load <2 x i8>* @i8_src1
|
||||||
%2 = load <2 x i8>* @i8_src2
|
%2 = load <2 x i8>* @i8_src2
|
||||||
%3 = add <2 x i8> %1, %2
|
%3 = add <2 x i8> %1, %2
|
||||||
@ -15,7 +15,7 @@ define void @test_neon_vector_add_2xi8() nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_neon_ld_st_volatile_with_ashr_2xi8() {
|
define void @test_neon_ld_st_volatile_with_ashr_2xi8() {
|
||||||
; CHECK: test_neon_ld_st_volatile_with_ashr_2xi8:
|
; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8:
|
||||||
%1 = load volatile <2 x i8>* @i8_src1
|
%1 = load volatile <2 x i8>* @i8_src1
|
||||||
%2 = load volatile <2 x i8>* @i8_src2
|
%2 = load volatile <2 x i8>* @i8_src2
|
||||||
%3 = ashr <2 x i8> %1, %2
|
%3 = ashr <2 x i8> %1, %2
|
||||||
|
|||||||
@ -7,7 +7,7 @@
|
|||||||
declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind
|
declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind
|
||||||
|
|
||||||
define void @test_neon_call_return_v2i16() {
|
define void @test_neon_call_return_v2i16() {
|
||||||
; CHECK: test_neon_call_return_v2i16:
|
; CHECK-LABEL: test_neon_call_return_v2i16:
|
||||||
%1 = load <2 x i16>* @src1_v2i16
|
%1 = load <2 x i16>* @src1_v2i16
|
||||||
%2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind
|
%2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind
|
||||||
store <2 x i16> %2, <2 x i16>* @res_v2i16
|
store <2 x i16> %2, <2 x i16>* @res_v2i16
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
|
|
||||||
define void @test_sqrt(<4 x float>* %X) nounwind {
|
define void @test_sqrt(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_sqrt:
|
; CHECK-LABEL: test_sqrt:
|
||||||
|
|
||||||
; CHECK: movw r1, :lower16:{{.*}}
|
; CHECK: movw r1, :lower16:{{.*}}
|
||||||
; CHECK: movt r1, :upper16:{{.*}}
|
; CHECK: movt r1, :upper16:{{.*}}
|
||||||
@ -27,7 +27,7 @@ declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
|
|||||||
|
|
||||||
define void @test_cos(<4 x float>* %X) nounwind {
|
define void @test_cos(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_cos:
|
; CHECK-LABEL: test_cos:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
@ -58,7 +58,7 @@ declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
|
|||||||
|
|
||||||
define void @test_exp(<4 x float>* %X) nounwind {
|
define void @test_exp(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_exp:
|
; CHECK-LABEL: test_exp:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
@ -89,7 +89,7 @@ declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
|
|||||||
|
|
||||||
define void @test_exp2(<4 x float>* %X) nounwind {
|
define void @test_exp2(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_exp2:
|
; CHECK-LABEL: test_exp2:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
@ -120,7 +120,7 @@ declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
|
|||||||
|
|
||||||
define void @test_log10(<4 x float>* %X) nounwind {
|
define void @test_log10(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_log10:
|
; CHECK-LABEL: test_log10:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
@ -151,7 +151,7 @@ declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
|
|||||||
|
|
||||||
define void @test_log(<4 x float>* %X) nounwind {
|
define void @test_log(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_log:
|
; CHECK-LABEL: test_log:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
@ -182,7 +182,7 @@ declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
|
|||||||
|
|
||||||
define void @test_log2(<4 x float>* %X) nounwind {
|
define void @test_log2(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_log2:
|
; CHECK-LABEL: test_log2:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
@ -214,7 +214,7 @@ declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
|
|||||||
|
|
||||||
define void @test_pow(<4 x float>* %X) nounwind {
|
define void @test_pow(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_pow:
|
; CHECK-LABEL: test_pow:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
@ -248,7 +248,7 @@ declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
|
|||||||
|
|
||||||
define void @test_powi(<4 x float>* %X) nounwind {
|
define void @test_powi(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_powi:
|
; CHECK-LABEL: test_powi:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
@ -271,7 +271,7 @@ declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
|
|||||||
|
|
||||||
define void @test_sin(<4 x float>* %X) nounwind {
|
define void @test_sin(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_sin:
|
; CHECK-LABEL: test_sin:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
@ -302,7 +302,7 @@ declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
|
|||||||
|
|
||||||
define void @test_floor(<4 x float>* %X) nounwind {
|
define void @test_floor(<4 x float>* %X) nounwind {
|
||||||
|
|
||||||
; CHECK: test_floor:
|
; CHECK-LABEL: test_floor:
|
||||||
|
|
||||||
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
|
||||||
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
; CHECK: movt [[reg0]], :upper16:{{.*}}
|
||||||
|
|||||||
@ -12,7 +12,7 @@
|
|||||||
@var_v2i64 = global <2 x i64> zeroinitializer
|
@var_v2i64 = global <2 x i64> zeroinitializer
|
||||||
|
|
||||||
define void @test_v2i8tov2i32() {
|
define void @test_v2i8tov2i32() {
|
||||||
; CHECK: test_v2i8tov2i32:
|
; CHECK-LABEL: test_v2i8tov2i32:
|
||||||
|
|
||||||
%i8val = load <2 x i8>* @var_v2i8
|
%i8val = load <2 x i8>* @var_v2i8
|
||||||
|
|
||||||
@ -26,7 +26,7 @@ define void @test_v2i8tov2i32() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_v2i8tov2i64() {
|
define void @test_v2i8tov2i64() {
|
||||||
; CHECK: test_v2i8tov2i64:
|
; CHECK-LABEL: test_v2i8tov2i64:
|
||||||
|
|
||||||
%i8val = load <2 x i8>* @var_v2i8
|
%i8val = load <2 x i8>* @var_v2i8
|
||||||
|
|
||||||
@ -44,7 +44,7 @@ define void @test_v2i8tov2i64() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_v4i8tov4i16() {
|
define void @test_v4i8tov4i16() {
|
||||||
; CHECK: test_v4i8tov4i16:
|
; CHECK-LABEL: test_v4i8tov4i16:
|
||||||
|
|
||||||
%i8val = load <4 x i8>* @var_v4i8
|
%i8val = load <4 x i8>* @var_v4i8
|
||||||
|
|
||||||
@ -59,7 +59,7 @@ define void @test_v4i8tov4i16() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_v4i8tov4i32() {
|
define void @test_v4i8tov4i32() {
|
||||||
; CHECK: test_v4i8tov4i32:
|
; CHECK-LABEL: test_v4i8tov4i32:
|
||||||
|
|
||||||
%i8val = load <4 x i8>* @var_v4i8
|
%i8val = load <4 x i8>* @var_v4i8
|
||||||
|
|
||||||
@ -73,7 +73,7 @@ define void @test_v4i8tov4i32() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_v2i16tov2i32() {
|
define void @test_v2i16tov2i32() {
|
||||||
; CHECK: test_v2i16tov2i32:
|
; CHECK-LABEL: test_v2i16tov2i32:
|
||||||
|
|
||||||
%i16val = load <2 x i16>* @var_v2i16
|
%i16val = load <2 x i16>* @var_v2i16
|
||||||
|
|
||||||
@ -88,7 +88,7 @@ define void @test_v2i16tov2i32() {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_v2i16tov2i64() {
|
define void @test_v2i16tov2i64() {
|
||||||
; CHECK: test_v2i16tov2i64:
|
; CHECK-LABEL: test_v2i16tov2i64:
|
||||||
|
|
||||||
%i16val = load <2 x i16>* @var_v2i16
|
%i16val = load <2 x i16>* @var_v2i16
|
||||||
|
|
||||||
|
|||||||
@ -7,7 +7,7 @@
|
|||||||
declare void @llvm.va_start(i8*) nounwind
|
declare void @llvm.va_start(i8*) nounwind
|
||||||
declare void @llvm.va_end(i8*) nounwind
|
declare void @llvm.va_end(i8*) nounwind
|
||||||
|
|
||||||
; CHECK: test_byval_8_bytes_alignment:
|
; CHECK-LABEL: test_byval_8_bytes_alignment:
|
||||||
define void @test_byval_8_bytes_alignment(i32 %i, ...) {
|
define void @test_byval_8_bytes_alignment(i32 %i, ...) {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: stm r0, {r1, r2, r3}
|
; CHECK: stm r0, {r1, r2, r3}
|
||||||
@ -40,7 +40,7 @@ entry:
|
|||||||
|
|
||||||
declare void @f(double);
|
declare void @f(double);
|
||||||
|
|
||||||
; CHECK: test_byval_8_bytes_alignment_fixed_arg:
|
; CHECK-LABEL: test_byval_8_bytes_alignment_fixed_arg:
|
||||||
; CHECK-NOT: str r1
|
; CHECK-NOT: str r1
|
||||||
; CHECK: str r3, [sp, #12]
|
; CHECK: str r3, [sp, #12]
|
||||||
; CHECK: str r2, [sp, #8]
|
; CHECK: str r2, [sp, #8]
|
||||||
|
|||||||
@ -6,7 +6,7 @@
|
|||||||
|
|
||||||
declare i32 @printf(i8*, ...)
|
declare i32 @printf(i8*, ...)
|
||||||
|
|
||||||
; CHECK: test_byval_usage_scheduling:
|
; CHECK-LABEL: test_byval_usage_scheduling:
|
||||||
; CHECK: str r3, [sp, #12]
|
; CHECK: str r3, [sp, #12]
|
||||||
; CHECK: str r2, [sp, #8]
|
; CHECK: str r2, [sp, #8]
|
||||||
; CHECK: vldr d16, [sp, #8]
|
; CHECK: vldr d16, [sp, #8]
|
||||||
|
|||||||
@ -2,7 +2,7 @@
|
|||||||
; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB
|
; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB
|
||||||
|
|
||||||
define i64 @test1(i64* %ptr, i64 %val) {
|
define i64 @test1(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test1:
|
; CHECK-LABEL: test1:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||||
@ -27,7 +27,7 @@ define i64 @test1(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test2(i64* %ptr, i64 %val) {
|
define i64 @test2(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test2:
|
; CHECK-LABEL: test2:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||||
@ -52,7 +52,7 @@ define i64 @test2(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test3(i64* %ptr, i64 %val) {
|
define i64 @test3(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test3:
|
; CHECK-LABEL: test3:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||||
@ -77,7 +77,7 @@ define i64 @test3(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test4(i64* %ptr, i64 %val) {
|
define i64 @test4(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test4:
|
; CHECK-LABEL: test4:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||||
@ -102,7 +102,7 @@ define i64 @test4(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test5(i64* %ptr, i64 %val) {
|
define i64 @test5(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test5:
|
; CHECK-LABEL: test5:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
|
||||||
@ -127,7 +127,7 @@ define i64 @test5(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test6(i64* %ptr, i64 %val) {
|
define i64 @test6(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test6:
|
; CHECK-LABEL: test6:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
|
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
|
||||||
@ -148,7 +148,7 @@ define i64 @test6(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
|
define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
|
||||||
; CHECK: test7:
|
; CHECK-LABEL: test7:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: cmp [[REG1]]
|
; CHECK: cmp [[REG1]]
|
||||||
@ -178,7 +178,7 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
|
|||||||
; Compiles down to cmpxchg
|
; Compiles down to cmpxchg
|
||||||
; FIXME: Should compile to a single ldrexd
|
; FIXME: Should compile to a single ldrexd
|
||||||
define i64 @test8(i64* %ptr) {
|
define i64 @test8(i64* %ptr) {
|
||||||
; CHECK: test8:
|
; CHECK-LABEL: test8:
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: cmp [[REG1]]
|
; CHECK: cmp [[REG1]]
|
||||||
; CHECK: cmpeq [[REG2]]
|
; CHECK: cmpeq [[REG2]]
|
||||||
@ -206,7 +206,7 @@ define i64 @test8(i64* %ptr) {
|
|||||||
; Compiles down to atomicrmw xchg; there really isn't any more efficient
|
; Compiles down to atomicrmw xchg; there really isn't any more efficient
|
||||||
; way to write it.
|
; way to write it.
|
||||||
define void @test9(i64* %ptr, i64 %val) {
|
define void @test9(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test9:
|
; CHECK-LABEL: test9:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
|
; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
|
||||||
@ -227,7 +227,7 @@ define void @test9(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test10(i64* %ptr, i64 %val) {
|
define i64 @test10(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test10:
|
; CHECK-LABEL: test10:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
|
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
|
||||||
@ -254,7 +254,7 @@ define i64 @test10(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test11(i64* %ptr, i64 %val) {
|
define i64 @test11(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test11:
|
; CHECK-LABEL: test11:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
|
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
|
||||||
@ -282,7 +282,7 @@ define i64 @test11(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test12(i64* %ptr, i64 %val) {
|
define i64 @test12(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test12:
|
; CHECK-LABEL: test12:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
|
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
|
||||||
@ -309,7 +309,7 @@ define i64 @test12(i64* %ptr, i64 %val) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i64 @test13(i64* %ptr, i64 %val) {
|
define i64 @test13(i64* %ptr, i64 %val) {
|
||||||
; CHECK: test13:
|
; CHECK-LABEL: test13:
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||||
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
|
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
|
||||||
|
|||||||
@ -7,4 +7,4 @@ define void @f(<4 x i8> %param1, <4 x i8> %param2) {
|
|||||||
%z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
|
%z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
|
||||||
call void @g(<16 x i8> %z)
|
call void @g(<16 x i8> %z)
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s
|
; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s
|
||||||
|
|
||||||
; PR15525
|
; PR15525
|
||||||
; CHECK: test1:
|
; CHECK-LABEL: test1:
|
||||||
; CHECK: ldr.w [[REG:r[0-9]+]], [sp]
|
; CHECK: ldr.w [[REG:r[0-9]+]], [sp]
|
||||||
; CHECK-NEXT: vmov {{d[0-9]+}}, r1, r2
|
; CHECK-NEXT: vmov {{d[0-9]+}}, r1, r2
|
||||||
; CHECK-NEXT: vmov {{d[0-9]+}}, r3, [[REG]]
|
; CHECK-NEXT: vmov {{d[0-9]+}}, r3, [[REG]]
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc -verify-machineinstrs -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s
|
; RUN: llc -verify-machineinstrs -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s
|
||||||
|
|
||||||
define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {
|
define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {
|
||||||
; CHECK: test_vmovs_via_vext_lane0to0:
|
; CHECK-LABEL: test_vmovs_via_vext_lane0to0:
|
||||||
%vec = insertelement <2 x float> %in, float %arg, i32 0
|
%vec = insertelement <2 x float> %in, float %arg, i32 0
|
||||||
%res = fadd <2 x float> %vec, %vec
|
%res = fadd <2 x float> %vec, %vec
|
||||||
|
|
||||||
@ -13,7 +13,7 @@ define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {
|
define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {
|
||||||
; CHECK: test_vmovs_via_vext_lane0to1:
|
; CHECK-LABEL: test_vmovs_via_vext_lane0to1:
|
||||||
%vec = insertelement <2 x float> %in, float %arg, i32 1
|
%vec = insertelement <2 x float> %in, float %arg, i32 1
|
||||||
%res = fadd <2 x float> %vec, %vec
|
%res = fadd <2 x float> %vec, %vec
|
||||||
|
|
||||||
@ -25,7 +25,7 @@ define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float> %in) {
|
define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float> %in) {
|
||||||
; CHECK: test_vmovs_via_vext_lane1to0:
|
; CHECK-LABEL: test_vmovs_via_vext_lane1to0:
|
||||||
%vec = insertelement <2 x float> %in, float %arg, i32 0
|
%vec = insertelement <2 x float> %in, float %arg, i32 0
|
||||||
%res = fadd <2 x float> %vec, %vec
|
%res = fadd <2 x float> %vec, %vec
|
||||||
|
|
||||||
@ -37,7 +37,7 @@ define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float>
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float> %in) {
|
define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float> %in) {
|
||||||
; CHECK: test_vmovs_via_vext_lane1to1:
|
; CHECK-LABEL: test_vmovs_via_vext_lane1to1:
|
||||||
%vec = insertelement <2 x float> %in, float %arg, i32 1
|
%vec = insertelement <2 x float> %in, float %arg, i32 1
|
||||||
%res = fadd <2 x float> %vec, %vec
|
%res = fadd <2 x float> %vec, %vec
|
||||||
|
|
||||||
@ -50,7 +50,7 @@ define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float>
|
|||||||
|
|
||||||
|
|
||||||
define float @test_vmovs_via_vdup(float, float %ret, float %lhs, float %rhs) {
|
define float @test_vmovs_via_vdup(float, float %ret, float %lhs, float %rhs) {
|
||||||
; CHECK: test_vmovs_via_vdup:
|
; CHECK-LABEL: test_vmovs_via_vdup:
|
||||||
|
|
||||||
; Do an operation (which will end up NEON because of +neonfp) to convince the
|
; Do an operation (which will end up NEON because of +neonfp) to convince the
|
||||||
; execution-domain pass that NEON is a good thing to use.
|
; execution-domain pass that NEON is a good thing to use.
|
||||||
@ -68,7 +68,7 @@ declare void @bar()
|
|||||||
|
|
||||||
; This is a comp
|
; This is a comp
|
||||||
define float @test_ineligible(float, float %in) {
|
define float @test_ineligible(float, float %in) {
|
||||||
; CHECK: test_ineligible:
|
; CHECK-LABEL: test_ineligible:
|
||||||
|
|
||||||
%sqrt = call float @llvm.sqrt.f32(float %in)
|
%sqrt = call float @llvm.sqrt.f32(float %in)
|
||||||
%val = fadd float %sqrt, %sqrt
|
%val = fadd float %sqrt, %sqrt
|
||||||
@ -85,7 +85,7 @@ define float @test_ineligible(float, float %in) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_vmovs_no_sreg(i32 %in) {
|
define i32 @test_vmovs_no_sreg(i32 %in) {
|
||||||
; CHECK: test_vmovs_no_sreg:
|
; CHECK-LABEL: test_vmovs_no_sreg:
|
||||||
|
|
||||||
; Check that the movement to and from GPRs takes place in the NEON domain.
|
; Check that the movement to and from GPRs takes place in the NEON domain.
|
||||||
; CHECK: vmov.32 d
|
; CHECK: vmov.32 d
|
||||||
|
|||||||
@ -1,6 +1,6 @@
|
|||||||
; RUN: llc < %s -mtriple=armv7-eabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s
|
; RUN: llc < %s -mtriple=armv7-eabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s
|
||||||
|
|
||||||
; CHECK: test:
|
; CHECK-LABEL: test:
|
||||||
; CHECK: vabs.f32 q0, q0
|
; CHECK: vabs.f32 q0, q0
|
||||||
define <4 x float> @test(<4 x float> %a) {
|
define <4 x float> @test(<4 x float> %a) {
|
||||||
%foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
|
%foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
|
||||||
@ -8,7 +8,7 @@ define <4 x float> @test(<4 x float> %a) {
|
|||||||
}
|
}
|
||||||
declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
|
declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
|
||||||
|
|
||||||
; CHECK: test2:
|
; CHECK-LABEL: test2:
|
||||||
; CHECK: vabs.f32 d0, d0
|
; CHECK: vabs.f32 d0, d0
|
||||||
define <2 x float> @test2(<2 x float> %a) {
|
define <2 x float> @test2(<2 x float> %a) {
|
||||||
%foo = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
|
%foo = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
|
||||||
|
|||||||
@ -13,17 +13,17 @@ entry:
|
|||||||
|
|
||||||
declare float @fabsf(float)
|
declare float @fabsf(float)
|
||||||
|
|
||||||
; VFP2: test:
|
; VFP2-LABEL: test:
|
||||||
; VFP2: vabs.f32 s
|
; VFP2: vabs.f32 s
|
||||||
|
|
||||||
; NFP1: test:
|
; NFP1-LABEL: test:
|
||||||
; NFP1: vabs.f32 d
|
; NFP1: vabs.f32 d
|
||||||
; NFP0: test:
|
; NFP0-LABEL: test:
|
||||||
; NFP0: vabs.f32 s
|
; NFP0: vabs.f32 s
|
||||||
|
|
||||||
; CORTEXA8: test:
|
; CORTEXA8-LABEL: test:
|
||||||
; CORTEXA8: vadd.f32 [[D1:d[0-9]+]]
|
; CORTEXA8: vadd.f32 [[D1:d[0-9]+]]
|
||||||
; CORTEXA8: vabs.f32 {{d[0-9]+}}, [[D1]]
|
; CORTEXA8: vabs.f32 {{d[0-9]+}}, [[D1]]
|
||||||
|
|
||||||
; CORTEXA9: test:
|
; CORTEXA9-LABEL: test:
|
||||||
; CORTEXA9: vabs.f32 s{{.}}, s{{.}}
|
; CORTEXA9: vabs.f32 s{{.}}, s{{.}}
|
||||||
|
|||||||
@ -11,17 +11,17 @@ entry:
|
|||||||
ret float %0
|
ret float %0
|
||||||
}
|
}
|
||||||
|
|
||||||
; VFP2: test:
|
; VFP2-LABEL: test:
|
||||||
; VFP2: vadd.f32 s
|
; VFP2: vadd.f32 s
|
||||||
|
|
||||||
; NFP1: test:
|
; NFP1-LABEL: test:
|
||||||
; NFP1: vadd.f32 d
|
; NFP1: vadd.f32 d
|
||||||
; NFP0: test:
|
; NFP0-LABEL: test:
|
||||||
; NFP0: vadd.f32 s
|
; NFP0: vadd.f32 s
|
||||||
|
|
||||||
; CORTEXA8: test:
|
; CORTEXA8-LABEL: test:
|
||||||
; CORTEXA8: vadd.f32 s
|
; CORTEXA8: vadd.f32 s
|
||||||
; CORTEXA8U: test:
|
; CORTEXA8U-LABEL: test:
|
||||||
; CORTEXA8U: vadd.f32 d
|
; CORTEXA8U: vadd.f32 d
|
||||||
; CORTEXA9: test:
|
; CORTEXA9-LABEL: test:
|
||||||
; CORTEXA9: vadd.f32 s
|
; CORTEXA9: vadd.f32 s
|
||||||
|
|||||||
@ -27,16 +27,16 @@ br label %if.end
|
|||||||
|
|
||||||
if.end: ; preds = %if.then, %entry
|
if.end: ; preds = %if.then, %entry
|
||||||
ret void
|
ret void
|
||||||
; ARM: test1:
|
; ARM-LABEL: test1:
|
||||||
; ARM: tst r0, #1
|
; ARM: tst r0, #1
|
||||||
; THUMB: test1:
|
; THUMB-LABEL: test1:
|
||||||
; THUMB: tst.w r0, #1
|
; THUMB: tst.w r0, #1
|
||||||
}
|
}
|
||||||
|
|
||||||
; Check some simple operations with immediates
|
; Check some simple operations with immediates
|
||||||
define void @test2(i32 %tmp, i32* %ptr) nounwind {
|
define void @test2(i32 %tmp, i32* %ptr) nounwind {
|
||||||
; THUMB: test2:
|
; THUMB-LABEL: test2:
|
||||||
; ARM: test2:
|
; ARM-LABEL: test2:
|
||||||
|
|
||||||
b1:
|
b1:
|
||||||
%a = add i32 %tmp, 4096
|
%a = add i32 %tmp, 4096
|
||||||
@ -64,8 +64,8 @@ b3:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind {
|
define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind {
|
||||||
; THUMB: test3:
|
; THUMB-LABEL: test3:
|
||||||
; ARM: test3:
|
; ARM-LABEL: test3:
|
||||||
|
|
||||||
bb1:
|
bb1:
|
||||||
%a1 = trunc i32 %tmp to i16
|
%a1 = trunc i32 %tmp to i16
|
||||||
|
|||||||
@ -4,11 +4,11 @@
|
|||||||
; rdar://8984306
|
; rdar://8984306
|
||||||
define float @test1(float %x, float %y) nounwind {
|
define float @test1(float %x, float %y) nounwind {
|
||||||
entry:
|
entry:
|
||||||
; SOFT: test1:
|
; SOFT-LABEL: test1:
|
||||||
; SOFT: lsr r1, r1, #31
|
; SOFT: lsr r1, r1, #31
|
||||||
; SOFT: bfi r0, r1, #31, #1
|
; SOFT: bfi r0, r1, #31, #1
|
||||||
|
|
||||||
; HARD: test1:
|
; HARD-LABEL: test1:
|
||||||
; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000
|
; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000
|
||||||
; HARD: vbsl [[REG1]], d
|
; HARD: vbsl [[REG1]], d
|
||||||
%0 = tail call float @copysignf(float %x, float %y) nounwind readnone
|
%0 = tail call float @copysignf(float %x, float %y) nounwind readnone
|
||||||
@ -17,11 +17,11 @@ entry:
|
|||||||
|
|
||||||
define double @test2(double %x, double %y) nounwind {
|
define double @test2(double %x, double %y) nounwind {
|
||||||
entry:
|
entry:
|
||||||
; SOFT: test2:
|
; SOFT-LABEL: test2:
|
||||||
; SOFT: lsr r2, r3, #31
|
; SOFT: lsr r2, r3, #31
|
||||||
; SOFT: bfi r1, r2, #31, #1
|
; SOFT: bfi r1, r2, #31, #1
|
||||||
|
|
||||||
; HARD: test2:
|
; HARD-LABEL: test2:
|
||||||
; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000
|
; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000
|
||||||
; HARD: vshl.i64 [[REG2]], [[REG2]], #32
|
; HARD: vshl.i64 [[REG2]], [[REG2]], #32
|
||||||
; HARD: vbsl [[REG2]], d1, d0
|
; HARD: vbsl [[REG2]], d1, d0
|
||||||
@ -31,7 +31,7 @@ entry:
|
|||||||
|
|
||||||
define double @test3(double %x, double %y, double %z) nounwind {
|
define double @test3(double %x, double %y, double %z) nounwind {
|
||||||
entry:
|
entry:
|
||||||
; SOFT: test3:
|
; SOFT-LABEL: test3:
|
||||||
; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000
|
; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000
|
||||||
; SOFT: vshl.i64 [[REG3]], [[REG3]], #32
|
; SOFT: vshl.i64 [[REG3]], [[REG3]], #32
|
||||||
; SOFT: vbsl [[REG3]],
|
; SOFT: vbsl [[REG3]],
|
||||||
@ -43,7 +43,7 @@ entry:
|
|||||||
; rdar://9287902
|
; rdar://9287902
|
||||||
define float @test4() nounwind {
|
define float @test4() nounwind {
|
||||||
entry:
|
entry:
|
||||||
; SOFT: test4:
|
; SOFT-LABEL: test4:
|
||||||
; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
|
; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
|
||||||
; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
|
; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
|
||||||
; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
|
; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
|
||||||
|
|||||||
@ -9,15 +9,15 @@ entry:
|
|||||||
ret float %0
|
ret float %0
|
||||||
}
|
}
|
||||||
|
|
||||||
; VFP2: test:
|
; VFP2-LABEL: test:
|
||||||
; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
||||||
|
|
||||||
; NFP1: test:
|
; NFP1-LABEL: test:
|
||||||
; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
||||||
; NFP0: test:
|
; NFP0-LABEL: test:
|
||||||
; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
||||||
|
|
||||||
; CORTEXA8: test:
|
; CORTEXA8-LABEL: test:
|
||||||
; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
||||||
; CORTEXA9: test:
|
; CORTEXA9-LABEL: test:
|
||||||
; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
|
||||||
|
|||||||
@ -11,19 +11,19 @@ entry:
|
|||||||
ret float %0
|
ret float %0
|
||||||
}
|
}
|
||||||
|
|
||||||
; VFP2: test:
|
; VFP2-LABEL: test:
|
||||||
; VFP2: vmul.f32 s
|
; VFP2: vmul.f32 s
|
||||||
|
|
||||||
; NFP1: test:
|
; NFP1-LABEL: test:
|
||||||
; NFP1: vmul.f32 d
|
; NFP1: vmul.f32 d
|
||||||
; NFP0: test:
|
; NFP0-LABEL: test:
|
||||||
; NFP0: vmul.f32 s
|
; NFP0: vmul.f32 s
|
||||||
|
|
||||||
; CORTEXA8: test:
|
; CORTEXA8-LABEL: test:
|
||||||
; CORTEXA8: vmul.f32 s
|
; CORTEXA8: vmul.f32 s
|
||||||
; CORTEXA8U: test:
|
; CORTEXA8U-LABEL: test:
|
||||||
; CORTEXA8U: vmul.f32 d
|
; CORTEXA8U: vmul.f32 d
|
||||||
; CORTEXA9: test:
|
; CORTEXA9-LABEL: test:
|
||||||
; CORTEXA9: vmul.f32 s
|
; CORTEXA9: vmul.f32 s
|
||||||
|
|
||||||
; VFP2: test2
|
; VFP2: test2
|
||||||
|
|||||||
@ -14,22 +14,22 @@ entry:
|
|||||||
%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
|
%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
|
||||||
ret float %retval
|
ret float %retval
|
||||||
}
|
}
|
||||||
; VFP2: test1:
|
; VFP2-LABEL: test1:
|
||||||
; VFP2: vneg.f32 s{{.*}}, s{{.*}}
|
; VFP2: vneg.f32 s{{.*}}, s{{.*}}
|
||||||
|
|
||||||
; NFP1: test1:
|
; NFP1-LABEL: test1:
|
||||||
; NFP1: vneg.f32 d{{.*}}, d{{.*}}
|
; NFP1: vneg.f32 d{{.*}}, d{{.*}}
|
||||||
|
|
||||||
; NFP0: test1:
|
; NFP0-LABEL: test1:
|
||||||
; NFP0: vneg.f32 s{{.*}}, s{{.*}}
|
; NFP0: vneg.f32 s{{.*}}, s{{.*}}
|
||||||
|
|
||||||
; CORTEXA8: test1:
|
; CORTEXA8-LABEL: test1:
|
||||||
; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}}
|
; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}}
|
||||||
|
|
||||||
; CORTEXA8U: test1:
|
; CORTEXA8U-LABEL: test1:
|
||||||
; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}}
|
; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}}
|
||||||
|
|
||||||
; CORTEXA9: test1:
|
; CORTEXA9-LABEL: test1:
|
||||||
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
|
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
|
||||||
|
|
||||||
define float @test2(float* %a) {
|
define float @test2(float* %a) {
|
||||||
@ -41,21 +41,21 @@ entry:
|
|||||||
%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
|
%retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
|
||||||
ret float %retval
|
ret float %retval
|
||||||
}
|
}
|
||||||
; VFP2: test2:
|
; VFP2-LABEL: test2:
|
||||||
; VFP2: vneg.f32 s{{.*}}, s{{.*}}
|
; VFP2: vneg.f32 s{{.*}}, s{{.*}}
|
||||||
|
|
||||||
; NFP1: test2:
|
; NFP1-LABEL: test2:
|
||||||
; NFP1: vneg.f32 d{{.*}}, d{{.*}}
|
; NFP1: vneg.f32 d{{.*}}, d{{.*}}
|
||||||
|
|
||||||
; NFP0: test2:
|
; NFP0-LABEL: test2:
|
||||||
; NFP0: vneg.f32 s{{.*}}, s{{.*}}
|
; NFP0: vneg.f32 s{{.*}}, s{{.*}}
|
||||||
|
|
||||||
; CORTEXA8: test2:
|
; CORTEXA8-LABEL: test2:
|
||||||
; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}}
|
; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}}
|
||||||
|
|
||||||
; CORTEXA8U: test2:
|
; CORTEXA8U-LABEL: test2:
|
||||||
; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}}
|
; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}}
|
||||||
|
|
||||||
; CORTEXA9: test2:
|
; CORTEXA9-LABEL: test2:
|
||||||
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
|
; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
|
||||||
|
|
||||||
|
|||||||
@ -6,9 +6,9 @@
|
|||||||
; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
|
; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
|
||||||
|
|
||||||
define i32 @test1(float %a, float %b) {
|
define i32 @test1(float %a, float %b) {
|
||||||
; VFP2: test1:
|
; VFP2-LABEL: test1:
|
||||||
; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
|
; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
|
||||||
; NEON: test1:
|
; NEON-LABEL: test1:
|
||||||
; NEON: vadd.f32 [[D0:d[0-9]+]]
|
; NEON: vadd.f32 [[D0:d[0-9]+]]
|
||||||
; NEON: vcvt.s32.f32 d0, [[D0]]
|
; NEON: vcvt.s32.f32 d0, [[D0]]
|
||||||
entry:
|
entry:
|
||||||
@ -18,9 +18,9 @@ entry:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test2(float %a, float %b) {
|
define i32 @test2(float %a, float %b) {
|
||||||
; VFP2: test2:
|
; VFP2-LABEL: test2:
|
||||||
; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
|
; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
|
||||||
; NEON: test2:
|
; NEON-LABEL: test2:
|
||||||
; NEON: vadd.f32 [[D0:d[0-9]+]]
|
; NEON: vadd.f32 [[D0:d[0-9]+]]
|
||||||
; NEON: vcvt.u32.f32 d0, [[D0]]
|
; NEON: vcvt.u32.f32 d0, [[D0]]
|
||||||
entry:
|
entry:
|
||||||
@ -30,9 +30,9 @@ entry:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define float @test3(i32 %a, i32 %b) {
|
define float @test3(i32 %a, i32 %b) {
|
||||||
; VFP2: test3:
|
; VFP2-LABEL: test3:
|
||||||
; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
|
; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
|
||||||
; NEON: test3:
|
; NEON-LABEL: test3:
|
||||||
; NEON: vcvt.f32.u32 d
|
; NEON: vcvt.f32.u32 d
|
||||||
entry:
|
entry:
|
||||||
%0 = add i32 %a, %b
|
%0 = add i32 %a, %b
|
||||||
@ -41,9 +41,9 @@ entry:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define float @test4(i32 %a, i32 %b) {
|
define float @test4(i32 %a, i32 %b) {
|
||||||
; VFP2: test4:
|
; VFP2-LABEL: test4:
|
||||||
; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
|
; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
|
||||||
; NEON: test4:
|
; NEON-LABEL: test4:
|
||||||
; NEON: vcvt.f32.s32 d
|
; NEON: vcvt.f32.s32 d
|
||||||
entry:
|
entry:
|
||||||
%0 = add i32 %a, %b
|
%0 = add i32 %a, %b
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc < %s -march=arm | FileCheck %s
|
; RUN: llc < %s -march=arm | FileCheck %s
|
||||||
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
|
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
|
||||||
|
|
||||||
; CHECK: test1:
|
; CHECK-LABEL: test1:
|
||||||
; CHECK: ldr {{.*, \[.*]}}, -r2
|
; CHECK: ldr {{.*, \[.*]}}, -r2
|
||||||
; CHECK-NOT: ldr
|
; CHECK-NOT: ldr
|
||||||
define i32 @test1(i32 %a, i32 %b, i32 %c) {
|
define i32 @test1(i32 %a, i32 %b, i32 %c) {
|
||||||
@ -13,7 +13,7 @@ define i32 @test1(i32 %a, i32 %b, i32 %c) {
|
|||||||
ret i32 %tmp5
|
ret i32 %tmp5
|
||||||
}
|
}
|
||||||
|
|
||||||
; CHECK: test2:
|
; CHECK-LABEL: test2:
|
||||||
; CHECK: ldr {{.*, \[.*\]}}, #-16
|
; CHECK: ldr {{.*, \[.*\]}}, #-16
|
||||||
; CHECK-NOT: ldr
|
; CHECK-NOT: ldr
|
||||||
define i32 @test2(i32 %a, i32 %b) {
|
define i32 @test2(i32 %a, i32 %b) {
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc < %s -march=arm | FileCheck %s
|
; RUN: llc < %s -march=arm | FileCheck %s
|
||||||
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
|
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
|
||||||
|
|
||||||
; CHECK: test1:
|
; CHECK-LABEL: test1:
|
||||||
; CHECK: ldr {{.*!}}
|
; CHECK: ldr {{.*!}}
|
||||||
; CHECK-NOT: ldr
|
; CHECK-NOT: ldr
|
||||||
define i32* @test1(i32* %X, i32* %dest) {
|
define i32* @test1(i32* %X, i32* %dest) {
|
||||||
@ -11,7 +11,7 @@ define i32* @test1(i32* %X, i32* %dest) {
|
|||||||
ret i32* %Y
|
ret i32* %Y
|
||||||
}
|
}
|
||||||
|
|
||||||
; CHECK: test2:
|
; CHECK-LABEL: test2:
|
||||||
; CHECK: ldr {{.*!}}
|
; CHECK: ldr {{.*!}}
|
||||||
; CHECK-NOT: ldr
|
; CHECK-NOT: ldr
|
||||||
define i32 @test2(i32 %a, i32 %b, i32 %c) {
|
define i32 @test2(i32 %a, i32 %b, i32 %c) {
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
|
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
|
||||||
|
|
||||||
define <4 x i32> @test1(<4 x i32> %a) nounwind {
|
define <4 x i32> @test1(<4 x i32> %a) nounwind {
|
||||||
; CHECK: test1:
|
; CHECK-LABEL: test1:
|
||||||
; CHECK: vabs.s32 q
|
; CHECK: vabs.s32 q
|
||||||
%tmp1neg = sub <4 x i32> zeroinitializer, %a
|
%tmp1neg = sub <4 x i32> zeroinitializer, %a
|
||||||
%b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
|
%b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||||
@ -10,7 +10,7 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <4 x i32> @test2(<4 x i32> %a) nounwind {
|
define <4 x i32> @test2(<4 x i32> %a) nounwind {
|
||||||
; CHECK: test2:
|
; CHECK-LABEL: test2:
|
||||||
; CHECK: vabs.s32 q
|
; CHECK: vabs.s32 q
|
||||||
%tmp1neg = sub <4 x i32> zeroinitializer, %a
|
%tmp1neg = sub <4 x i32> zeroinitializer, %a
|
||||||
%b = icmp sge <4 x i32> %a, zeroinitializer
|
%b = icmp sge <4 x i32> %a, zeroinitializer
|
||||||
@ -19,7 +19,7 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i16> @test3(<8 x i16> %a) nounwind {
|
define <8 x i16> @test3(<8 x i16> %a) nounwind {
|
||||||
; CHECK: test3:
|
; CHECK-LABEL: test3:
|
||||||
; CHECK: vabs.s16 q
|
; CHECK: vabs.s16 q
|
||||||
%tmp1neg = sub <8 x i16> zeroinitializer, %a
|
%tmp1neg = sub <8 x i16> zeroinitializer, %a
|
||||||
%b = icmp sgt <8 x i16> %a, zeroinitializer
|
%b = icmp sgt <8 x i16> %a, zeroinitializer
|
||||||
@ -28,7 +28,7 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <16 x i8> @test4(<16 x i8> %a) nounwind {
|
define <16 x i8> @test4(<16 x i8> %a) nounwind {
|
||||||
; CHECK: test4:
|
; CHECK-LABEL: test4:
|
||||||
; CHECK: vabs.s8 q
|
; CHECK: vabs.s8 q
|
||||||
%tmp1neg = sub <16 x i8> zeroinitializer, %a
|
%tmp1neg = sub <16 x i8> zeroinitializer, %a
|
||||||
%b = icmp slt <16 x i8> %a, zeroinitializer
|
%b = icmp slt <16 x i8> %a, zeroinitializer
|
||||||
@ -37,7 +37,7 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <4 x i32> @test5(<4 x i32> %a) nounwind {
|
define <4 x i32> @test5(<4 x i32> %a) nounwind {
|
||||||
; CHECK: test5:
|
; CHECK-LABEL: test5:
|
||||||
; CHECK: vabs.s32 q
|
; CHECK: vabs.s32 q
|
||||||
%tmp1neg = sub <4 x i32> zeroinitializer, %a
|
%tmp1neg = sub <4 x i32> zeroinitializer, %a
|
||||||
%b = icmp sle <4 x i32> %a, zeroinitializer
|
%b = icmp sle <4 x i32> %a, zeroinitializer
|
||||||
@ -46,7 +46,7 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <2 x i32> @test6(<2 x i32> %a) nounwind {
|
define <2 x i32> @test6(<2 x i32> %a) nounwind {
|
||||||
; CHECK: test6:
|
; CHECK-LABEL: test6:
|
||||||
; CHECK: vabs.s32 d
|
; CHECK: vabs.s32 d
|
||||||
%tmp1neg = sub <2 x i32> zeroinitializer, %a
|
%tmp1neg = sub <2 x i32> zeroinitializer, %a
|
||||||
%b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
|
%b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
|
||||||
@ -55,7 +55,7 @@ define <2 x i32> @test6(<2 x i32> %a) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <2 x i32> @test7(<2 x i32> %a) nounwind {
|
define <2 x i32> @test7(<2 x i32> %a) nounwind {
|
||||||
; CHECK: test7:
|
; CHECK-LABEL: test7:
|
||||||
; CHECK: vabs.s32 d
|
; CHECK: vabs.s32 d
|
||||||
%tmp1neg = sub <2 x i32> zeroinitializer, %a
|
%tmp1neg = sub <2 x i32> zeroinitializer, %a
|
||||||
%b = icmp sge <2 x i32> %a, zeroinitializer
|
%b = icmp sge <2 x i32> %a, zeroinitializer
|
||||||
@ -64,7 +64,7 @@ define <2 x i32> @test7(<2 x i32> %a) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <4 x i16> @test8(<4 x i16> %a) nounwind {
|
define <4 x i16> @test8(<4 x i16> %a) nounwind {
|
||||||
; CHECK: test8:
|
; CHECK-LABEL: test8:
|
||||||
; CHECK: vabs.s16 d
|
; CHECK: vabs.s16 d
|
||||||
%tmp1neg = sub <4 x i16> zeroinitializer, %a
|
%tmp1neg = sub <4 x i16> zeroinitializer, %a
|
||||||
%b = icmp sgt <4 x i16> %a, zeroinitializer
|
%b = icmp sgt <4 x i16> %a, zeroinitializer
|
||||||
@ -73,7 +73,7 @@ define <4 x i16> @test8(<4 x i16> %a) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i8> @test9(<8 x i8> %a) nounwind {
|
define <8 x i8> @test9(<8 x i8> %a) nounwind {
|
||||||
; CHECK: test9:
|
; CHECK-LABEL: test9:
|
||||||
; CHECK: vabs.s8 d
|
; CHECK: vabs.s8 d
|
||||||
%tmp1neg = sub <8 x i8> zeroinitializer, %a
|
%tmp1neg = sub <8 x i8> zeroinitializer, %a
|
||||||
%b = icmp slt <8 x i8> %a, zeroinitializer
|
%b = icmp slt <8 x i8> %a, zeroinitializer
|
||||||
@ -82,7 +82,7 @@ define <8 x i8> @test9(<8 x i8> %a) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <2 x i32> @test10(<2 x i32> %a) nounwind {
|
define <2 x i32> @test10(<2 x i32> %a) nounwind {
|
||||||
; CHECK: test10:
|
; CHECK-LABEL: test10:
|
||||||
; CHECK: vabs.s32 d
|
; CHECK: vabs.s32 d
|
||||||
%tmp1neg = sub <2 x i32> zeroinitializer, %a
|
%tmp1neg = sub <2 x i32> zeroinitializer, %a
|
||||||
%b = icmp sle <2 x i32> %a, zeroinitializer
|
%b = icmp sle <2 x i32> %a, zeroinitializer
|
||||||
|
|||||||
@ -90,7 +90,7 @@ define i32 @test8(i32 %X, i32 %Y) {
|
|||||||
ret i32 %tmp57
|
ret i32 %tmp57
|
||||||
}
|
}
|
||||||
|
|
||||||
; CHECK: test9:
|
; CHECK-LABEL: test9:
|
||||||
; CHECK: pkhtb r0, r0, r1, asr #16
|
; CHECK: pkhtb r0, r0, r1, asr #16
|
||||||
define i32 @test9(i32 %src1, i32 %src2) {
|
define i32 @test9(i32 %src1, i32 %src2) {
|
||||||
entry:
|
entry:
|
||||||
@ -100,7 +100,7 @@ entry:
|
|||||||
ret i32 %tmp3
|
ret i32 %tmp3
|
||||||
}
|
}
|
||||||
|
|
||||||
; CHECK: test10:
|
; CHECK-LABEL: test10:
|
||||||
; CHECK: pkhtb r0, r0, r1, asr #17
|
; CHECK: pkhtb r0, r0, r1, asr #17
|
||||||
define i32 @test10(i32 %src1, i32 %src2) {
|
define i32 @test10(i32 %src1, i32 %src2) {
|
||||||
entry:
|
entry:
|
||||||
|
|||||||
@ -32,7 +32,7 @@ define i32 @test2(i32 %X) nounwind {
|
|||||||
; rdar://9147637
|
; rdar://9147637
|
||||||
define i32 @test3(i16 zeroext %a) nounwind {
|
define i32 @test3(i16 zeroext %a) nounwind {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test3:
|
; CHECK-LABEL: test3:
|
||||||
; CHECK: revsh r0, r0
|
; CHECK: revsh r0, r0
|
||||||
%0 = tail call i16 @llvm.bswap.i16(i16 %a)
|
%0 = tail call i16 @llvm.bswap.i16(i16 %a)
|
||||||
%1 = sext i16 %0 to i32
|
%1 = sext i16 %0 to i32
|
||||||
@ -43,7 +43,7 @@ declare i16 @llvm.bswap.i16(i16) nounwind readnone
|
|||||||
|
|
||||||
define i32 @test4(i16 zeroext %a) nounwind {
|
define i32 @test4(i16 zeroext %a) nounwind {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test4:
|
; CHECK-LABEL: test4:
|
||||||
; CHECK: revsh r0, r0
|
; CHECK: revsh r0, r0
|
||||||
%conv = zext i16 %a to i32
|
%conv = zext i16 %a to i32
|
||||||
%shr9 = lshr i16 %a, 8
|
%shr9 = lshr i16 %a, 8
|
||||||
|
|||||||
@ -4,10 +4,10 @@
|
|||||||
|
|
||||||
|
|
||||||
define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
|
define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
|
||||||
; A8: test1:
|
; A8-LABEL: test1:
|
||||||
; A8: add r0, r0, r1, lsl r2
|
; A8: add r0, r0, r1, lsl r2
|
||||||
|
|
||||||
; A9: test1:
|
; A9-LABEL: test1:
|
||||||
; A9: add r0, r0, r1, lsl r2
|
; A9: add r0, r0, r1, lsl r2
|
||||||
%shift.upgrd.1 = zext i8 %sh to i32
|
%shift.upgrd.1 = zext i8 %sh to i32
|
||||||
%A = shl i32 %Y, %shift.upgrd.1
|
%A = shl i32 %Y, %shift.upgrd.1
|
||||||
@ -16,10 +16,10 @@ define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
|
define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
|
||||||
; A8: test2:
|
; A8-LABEL: test2:
|
||||||
; A8: bic r0, r0, r1, asr r2
|
; A8: bic r0, r0, r1, asr r2
|
||||||
|
|
||||||
; A9: test2:
|
; A9-LABEL: test2:
|
||||||
; A9: bic r0, r0, r1, asr r2
|
; A9: bic r0, r0, r1, asr r2
|
||||||
%shift.upgrd.2 = zext i8 %sh to i32
|
%shift.upgrd.2 = zext i8 %sh to i32
|
||||||
%A = ashr i32 %Y, %shift.upgrd.2
|
%A = ashr i32 %Y, %shift.upgrd.2
|
||||||
@ -30,12 +30,12 @@ define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
|
|||||||
|
|
||||||
define i32 @test3(i32 %base, i32 %base2, i32 %offset) {
|
define i32 @test3(i32 %base, i32 %base2, i32 %offset) {
|
||||||
entry:
|
entry:
|
||||||
; A8: test3:
|
; A8-LABEL: test3:
|
||||||
; A8: ldr r0, [r0, r2, lsl #2]
|
; A8: ldr r0, [r0, r2, lsl #2]
|
||||||
; A8: ldr r1, [r1, r2, lsl #2]
|
; A8: ldr r1, [r1, r2, lsl #2]
|
||||||
|
|
||||||
; lsl #2 is free
|
; lsl #2 is free
|
||||||
; A9: test3:
|
; A9-LABEL: test3:
|
||||||
; A9: ldr r0, [r0, r2, lsl #2]
|
; A9: ldr r0, [r0, r2, lsl #2]
|
||||||
; A9: ldr r1, [r1, r2, lsl #2]
|
; A9: ldr r1, [r1, r2, lsl #2]
|
||||||
%tmp1 = shl i32 %offset, 2
|
%tmp1 = shl i32 %offset, 2
|
||||||
@ -53,13 +53,13 @@ declare i8* @malloc(...)
|
|||||||
|
|
||||||
define fastcc void @test4(i16 %addr) nounwind {
|
define fastcc void @test4(i16 %addr) nounwind {
|
||||||
entry:
|
entry:
|
||||||
; A8: test4:
|
; A8-LABEL: test4:
|
||||||
; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
|
; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
|
||||||
; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
|
; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
|
||||||
; A8: str [[REG]], [r0, r1, lsl #2]
|
; A8: str [[REG]], [r0, r1, lsl #2]
|
||||||
; A8-NOT: str [[REG]], [r0]
|
; A8-NOT: str [[REG]], [r0]
|
||||||
|
|
||||||
; A9: test4:
|
; A9-LABEL: test4:
|
||||||
; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
|
; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
|
||||||
; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
|
; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
|
||||||
; A9: str [[REG]], [r0, r1, lsl #2]
|
; A9: str [[REG]], [r0, r1, lsl #2]
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc < %s -march=arm | FileCheck %s
|
; RUN: llc < %s -march=arm | FileCheck %s
|
||||||
|
|
||||||
define i16 @test1(i32* %X, i16* %A) {
|
define i16 @test1(i32* %X, i16* %A) {
|
||||||
; CHECK: test1:
|
; CHECK-LABEL: test1:
|
||||||
; CHECK: strh {{.*}}[{{.*}}], #-4
|
; CHECK: strh {{.*}}[{{.*}}], #-4
|
||||||
%Y = load i32* %X ; <i32> [#uses=1]
|
%Y = load i32* %X ; <i32> [#uses=1]
|
||||||
%tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1]
|
%tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1]
|
||||||
@ -12,7 +12,7 @@ define i16 @test1(i32* %X, i16* %A) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test2(i32* %X, i32* %A) {
|
define i32 @test2(i32* %X, i32* %A) {
|
||||||
; CHECK: test2:
|
; CHECK-LABEL: test2:
|
||||||
; CHECK: str {{.*}}[{{.*}}],
|
; CHECK: str {{.*}}[{{.*}}],
|
||||||
%Y = load i32* %X ; <i32> [#uses=1]
|
%Y = load i32* %X ; <i32> [#uses=1]
|
||||||
store i32 %Y, i32* %A
|
store i32 %Y, i32* %A
|
||||||
|
|||||||
@ -4,7 +4,7 @@
|
|||||||
; Release operations only need the store barrier provided by a "dmb ishst",
|
; Release operations only need the store barrier provided by a "dmb ishst",
|
||||||
|
|
||||||
define void @test_store_release(i32* %p, i32 %v) {
|
define void @test_store_release(i32* %p, i32 %v) {
|
||||||
; CHECK: test_store_release:
|
; CHECK-LABEL: test_store_release:
|
||||||
; CHECK: dmb ishst
|
; CHECK: dmb ishst
|
||||||
; CHECK: str
|
; CHECK: str
|
||||||
|
|
||||||
@ -17,7 +17,7 @@ define void @test_store_release(i32* %p, i32 %v) {
|
|||||||
; followed by an acquire does not get reordered. In that case a "dmb ishst" is
|
; followed by an acquire does not get reordered. In that case a "dmb ishst" is
|
||||||
; not adequate.
|
; not adequate.
|
||||||
define i32 @test_seq_cst(i32* %p, i32 %v) {
|
define i32 @test_seq_cst(i32* %p, i32 %v) {
|
||||||
; CHECK: test_seq_cst:
|
; CHECK-LABEL: test_seq_cst:
|
||||||
; CHECK: dmb ishst
|
; CHECK: dmb ishst
|
||||||
; CHECK: str
|
; CHECK: str
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
@ -35,7 +35,7 @@ define i32 @test_seq_cst(i32* %p, i32 %v) {
|
|||||||
; Also, pure acquire operations should definitely not have an ishst barrier.
|
; Also, pure acquire operations should definitely not have an ishst barrier.
|
||||||
|
|
||||||
define i32 @test_acq(i32* %addr) {
|
define i32 @test_acq(i32* %addr) {
|
||||||
; CHECK: test_acq:
|
; CHECK-LABEL: test_acq:
|
||||||
; CHECK: ldr
|
; CHECK: ldr
|
||||||
; CHECK: dmb {{ish$}}
|
; CHECK: dmb {{ish$}}
|
||||||
|
|
||||||
|
|||||||
@ -39,4 +39,4 @@ bb3:
|
|||||||
}
|
}
|
||||||
|
|
||||||
declare noalias i8* @strdup(i8* nocapture) nounwind
|
declare noalias i8* @strdup(i8* nocapture) nounwind
|
||||||
declare i32 @_called_func(i8*, i32*) nounwind
|
declare i32 @_called_func(i8*, i32*) nounwind
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
|
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
|
||||||
; Test that we correctly align elements when using va_arg
|
; Test that we correctly align elements when using va_arg
|
||||||
|
|
||||||
; CHECK: test1:
|
; CHECK-LABEL: test1:
|
||||||
; CHECK-NOT: bfc
|
; CHECK-NOT: bfc
|
||||||
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
|
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
|
||||||
; CHECK: bfc [[REG]], #0, #3
|
; CHECK: bfc [[REG]], #0, #3
|
||||||
@ -17,7 +17,7 @@ entry:
|
|||||||
ret i64 %0
|
ret i64 %0
|
||||||
}
|
}
|
||||||
|
|
||||||
; CHECK: test2:
|
; CHECK-LABEL: test2:
|
||||||
; CHECK-NOT: bfc
|
; CHECK-NOT: bfc
|
||||||
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
|
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
|
||||||
; CHECK: bfc [[REG]], #0, #3
|
; CHECK: bfc [[REG]], #0, #3
|
||||||
|
|||||||
@ -163,28 +163,28 @@ define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
|
define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
|
||||||
; CHECK: test_vbsl_s64:
|
; CHECK-LABEL: test_vbsl_s64:
|
||||||
; CHECK: vbsl d
|
; CHECK: vbsl d
|
||||||
%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
|
%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
|
||||||
ret <1 x i64> %vbsl3.i
|
ret <1 x i64> %vbsl3.i
|
||||||
}
|
}
|
||||||
|
|
||||||
define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
|
define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
|
||||||
; CHECK: test_vbsl_u64:
|
; CHECK-LABEL: test_vbsl_u64:
|
||||||
; CHECK: vbsl d
|
; CHECK: vbsl d
|
||||||
%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
|
%vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
|
||||||
ret <1 x i64> %vbsl3.i
|
ret <1 x i64> %vbsl3.i
|
||||||
}
|
}
|
||||||
|
|
||||||
define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
|
define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
|
||||||
; CHECK: test_vbslq_s64:
|
; CHECK-LABEL: test_vbslq_s64:
|
||||||
; CHECK: vbsl q
|
; CHECK: vbsl q
|
||||||
%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
|
%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
|
||||||
ret <2 x i64> %vbsl3.i
|
ret <2 x i64> %vbsl3.i
|
||||||
}
|
}
|
||||||
|
|
||||||
define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
|
define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
|
||||||
; CHECK: test_vbslq_u64:
|
; CHECK-LABEL: test_vbslq_u64:
|
||||||
; CHECK: vbsl q
|
; CHECK: vbsl q
|
||||||
%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
|
%vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
|
||||||
ret <2 x i64> %vbsl3.i
|
ret <2 x i64> %vbsl3.i
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
|
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
|
||||||
|
|
||||||
define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||||
;CHECK: test_vextd:
|
;CHECK-LABEL: test_vextd:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
%tmp1 = load <8 x i8>* %A
|
%tmp1 = load <8 x i8>* %A
|
||||||
%tmp2 = load <8 x i8>* %B
|
%tmp2 = load <8 x i8>* %B
|
||||||
@ -10,7 +10,7 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||||
;CHECK: test_vextRd:
|
;CHECK-LABEL: test_vextRd:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
%tmp1 = load <8 x i8>* %A
|
%tmp1 = load <8 x i8>* %A
|
||||||
%tmp2 = load <8 x i8>* %B
|
%tmp2 = load <8 x i8>* %B
|
||||||
@ -19,7 +19,7 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
||||||
;CHECK: test_vextq:
|
;CHECK-LABEL: test_vextq:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
%tmp1 = load <16 x i8>* %A
|
%tmp1 = load <16 x i8>* %A
|
||||||
%tmp2 = load <16 x i8>* %B
|
%tmp2 = load <16 x i8>* %B
|
||||||
@ -28,7 +28,7 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
||||||
;CHECK: test_vextRq:
|
;CHECK-LABEL: test_vextRq:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
%tmp1 = load <16 x i8>* %A
|
%tmp1 = load <16 x i8>* %A
|
||||||
%tmp2 = load <16 x i8>* %B
|
%tmp2 = load <16 x i8>* %B
|
||||||
@ -37,7 +37,7 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||||
;CHECK: test_vextd16:
|
;CHECK-LABEL: test_vextd16:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
%tmp1 = load <4 x i16>* %A
|
%tmp1 = load <4 x i16>* %A
|
||||||
%tmp2 = load <4 x i16>* %B
|
%tmp2 = load <4 x i16>* %B
|
||||||
@ -46,7 +46,7 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
|
define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
|
||||||
;CHECK: test_vextq32:
|
;CHECK-LABEL: test_vextq32:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
%tmp1 = load <4 x i32>* %A
|
%tmp1 = load <4 x i32>* %A
|
||||||
%tmp2 = load <4 x i32>* %B
|
%tmp2 = load <4 x i32>* %B
|
||||||
@ -57,7 +57,7 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
|
|||||||
; Undef shuffle indices should not prevent matching to VEXT:
|
; Undef shuffle indices should not prevent matching to VEXT:
|
||||||
|
|
||||||
define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||||
;CHECK: test_vextd_undef:
|
;CHECK-LABEL: test_vextd_undef:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
%tmp1 = load <8 x i8>* %A
|
%tmp1 = load <8 x i8>* %A
|
||||||
%tmp2 = load <8 x i8>* %B
|
%tmp2 = load <8 x i8>* %B
|
||||||
@ -66,7 +66,7 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
||||||
;CHECK: test_vextRq_undef:
|
;CHECK-LABEL: test_vextRq_undef:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
%tmp1 = load <16 x i8>* %A
|
%tmp1 = load <16 x i8>* %A
|
||||||
%tmp2 = load <16 x i8>* %B
|
%tmp2 = load <16 x i8>* %B
|
||||||
@ -75,7 +75,7 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind {
|
define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind {
|
||||||
;CHECK: test_vextq_undef_op2:
|
;CHECK-LABEL: test_vextq_undef_op2:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
entry:
|
entry:
|
||||||
%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
|
%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
|
||||||
@ -83,7 +83,7 @@ entry:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind {
|
define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind {
|
||||||
;CHECK: test_vextd_undef_op2:
|
;CHECK-LABEL: test_vextd_undef_op2:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
entry:
|
entry:
|
||||||
%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
|
%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
|
||||||
@ -92,7 +92,7 @@ entry:
|
|||||||
|
|
||||||
|
|
||||||
define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind {
|
define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind {
|
||||||
;CHECK: test_vextq_undef_op2_undef:
|
;CHECK-LABEL: test_vextq_undef_op2_undef:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
entry:
|
entry:
|
||||||
%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
|
%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
|
||||||
@ -100,7 +100,7 @@ entry:
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind {
|
define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind {
|
||||||
;CHECK: test_vextd_undef_op2_undef:
|
;CHECK-LABEL: test_vextd_undef_op2_undef:
|
||||||
;CHECK: vext
|
;CHECK: vext
|
||||||
entry:
|
entry:
|
||||||
%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1>
|
%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1>
|
||||||
@ -114,7 +114,7 @@ entry:
|
|||||||
; Also checks interleaving of sources is handled correctly.
|
; Also checks interleaving of sources is handled correctly.
|
||||||
; Essence: a vext is used on %A and something saner than stack load/store for final result.
|
; Essence: a vext is used on %A and something saner than stack load/store for final result.
|
||||||
define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
||||||
;CHECK: test_interleaved:
|
;CHECK-LABEL: test_interleaved:
|
||||||
;CHECK: vext.16
|
;CHECK: vext.16
|
||||||
;CHECK-NOT: vext.16
|
;CHECK-NOT: vext.16
|
||||||
;CHECK: vzip.16
|
;CHECK: vzip.16
|
||||||
@ -126,7 +126,7 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
|||||||
|
|
||||||
; An undef in the shuffle list should still be optimizable
|
; An undef in the shuffle list should still be optimizable
|
||||||
define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
||||||
;CHECK: test_undef:
|
;CHECK-LABEL: test_undef:
|
||||||
;CHECK: vzip.16
|
;CHECK: vzip.16
|
||||||
%tmp1 = load <8 x i16>* %A
|
%tmp1 = load <8 x i16>* %A
|
||||||
%tmp2 = load <8 x i16>* %B
|
%tmp2 = load <8 x i16>* %B
|
||||||
@ -138,7 +138,7 @@ define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
|||||||
; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.
|
; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.
|
||||||
; Try to look for fallback to by-element inserts.
|
; Try to look for fallback to by-element inserts.
|
||||||
define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
|
define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
|
||||||
;CHECK: test_multisource:
|
;CHECK-LABEL: test_multisource:
|
||||||
;CHECK: vmov.16 [[REG:d[0-9]+]][0]
|
;CHECK: vmov.16 [[REG:d[0-9]+]][0]
|
||||||
;CHECK: vmov.16 [[REG]][1]
|
;CHECK: vmov.16 [[REG]][1]
|
||||||
;CHECK: vmov.16 [[REG]][2]
|
;CHECK: vmov.16 [[REG]][2]
|
||||||
@ -151,7 +151,7 @@ define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
|
|||||||
; We don't handle shuffles using more than half of a 128-bit vector.
|
; We don't handle shuffles using more than half of a 128-bit vector.
|
||||||
; Again, test for fallback to by-element inserts.
|
; Again, test for fallback to by-element inserts.
|
||||||
define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
|
define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
|
||||||
;CHECK: test_largespan:
|
;CHECK-LABEL: test_largespan:
|
||||||
;CHECK: vmov.16 [[REG:d[0-9]+]][0]
|
;CHECK: vmov.16 [[REG:d[0-9]+]][0]
|
||||||
;CHECK: vmov.16 [[REG]][1]
|
;CHECK: vmov.16 [[REG]][1]
|
||||||
;CHECK: vmov.16 [[REG]][2]
|
;CHECK: vmov.16 [[REG]][2]
|
||||||
@ -165,7 +165,7 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
|
|||||||
; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
|
; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
|
||||||
; lowering loop can result otherwise).
|
; lowering loop can result otherwise).
|
||||||
define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
||||||
;CHECK: test_illegal:
|
;CHECK-LABEL: test_illegal:
|
||||||
;CHECK: vmov.16 [[REG:d[0-9]+]][0]
|
;CHECK: vmov.16 [[REG:d[0-9]+]][0]
|
||||||
;CHECK: vmov.16 [[REG]][1]
|
;CHECK: vmov.16 [[REG]][1]
|
||||||
;CHECK: vmov.16 [[REG]][2]
|
;CHECK: vmov.16 [[REG]][2]
|
||||||
@ -183,7 +183,7 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
|||||||
; PR11129
|
; PR11129
|
||||||
; Make sure this doesn't crash
|
; Make sure this doesn't crash
|
||||||
define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
|
define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
|
||||||
; CHECK: test_elem_mismatch:
|
; CHECK-LABEL: test_elem_mismatch:
|
||||||
; CHECK: vstr
|
; CHECK: vstr
|
||||||
%tmp0 = load <2 x i64>* %src, align 16
|
%tmp0 = load <2 x i64>* %src, align 16
|
||||||
%tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
|
%tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
|
||||||
|
|||||||
@ -14,7 +14,7 @@ declare float @fabsf(float)
|
|||||||
declare double @fabs(double)
|
declare double @fabs(double)
|
||||||
|
|
||||||
define void @test_abs(float* %P, double* %D) {
|
define void @test_abs(float* %P, double* %D) {
|
||||||
;CHECK: test_abs:
|
;CHECK-LABEL: test_abs:
|
||||||
%a = load float* %P ; <float> [#uses=1]
|
%a = load float* %P ; <float> [#uses=1]
|
||||||
;CHECK: vabs.f32
|
;CHECK: vabs.f32
|
||||||
%b = call float @fabsf( float %a ) readnone ; <float> [#uses=1]
|
%b = call float @fabsf( float %a ) readnone ; <float> [#uses=1]
|
||||||
@ -27,7 +27,7 @@ define void @test_abs(float* %P, double* %D) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_add(float* %P, double* %D) {
|
define void @test_add(float* %P, double* %D) {
|
||||||
;CHECK: test_add:
|
;CHECK-LABEL: test_add:
|
||||||
%a = load float* %P ; <float> [#uses=2]
|
%a = load float* %P ; <float> [#uses=2]
|
||||||
%b = fadd float %a, %a ; <float> [#uses=1]
|
%b = fadd float %a, %a ; <float> [#uses=1]
|
||||||
store float %b, float* %P
|
store float %b, float* %P
|
||||||
@ -38,7 +38,7 @@ define void @test_add(float* %P, double* %D) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_ext_round(float* %P, double* %D) {
|
define void @test_ext_round(float* %P, double* %D) {
|
||||||
;CHECK: test_ext_round:
|
;CHECK-LABEL: test_ext_round:
|
||||||
%a = load float* %P ; <float> [#uses=1]
|
%a = load float* %P ; <float> [#uses=1]
|
||||||
;CHECK: vcvt.f64.f32
|
;CHECK: vcvt.f64.f32
|
||||||
;CHECK: vcvt.f32.f64
|
;CHECK: vcvt.f32.f64
|
||||||
@ -51,7 +51,7 @@ define void @test_ext_round(float* %P, double* %D) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_fma(float* %P1, float* %P2, float* %P3) {
|
define void @test_fma(float* %P1, float* %P2, float* %P3) {
|
||||||
;CHECK: test_fma:
|
;CHECK-LABEL: test_fma:
|
||||||
%a1 = load float* %P1 ; <float> [#uses=1]
|
%a1 = load float* %P1 ; <float> [#uses=1]
|
||||||
%a2 = load float* %P2 ; <float> [#uses=1]
|
%a2 = load float* %P2 ; <float> [#uses=1]
|
||||||
%a3 = load float* %P3 ; <float> [#uses=1]
|
%a3 = load float* %P3 ; <float> [#uses=1]
|
||||||
@ -63,7 +63,7 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_ftoi(float* %P1) {
|
define i32 @test_ftoi(float* %P1) {
|
||||||
;CHECK: test_ftoi:
|
;CHECK-LABEL: test_ftoi:
|
||||||
%a1 = load float* %P1 ; <float> [#uses=1]
|
%a1 = load float* %P1 ; <float> [#uses=1]
|
||||||
;CHECK: vcvt.s32.f32
|
;CHECK: vcvt.s32.f32
|
||||||
%b1 = fptosi float %a1 to i32 ; <i32> [#uses=1]
|
%b1 = fptosi float %a1 to i32 ; <i32> [#uses=1]
|
||||||
@ -71,7 +71,7 @@ define i32 @test_ftoi(float* %P1) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_ftou(float* %P1) {
|
define i32 @test_ftou(float* %P1) {
|
||||||
;CHECK: test_ftou:
|
;CHECK-LABEL: test_ftou:
|
||||||
%a1 = load float* %P1 ; <float> [#uses=1]
|
%a1 = load float* %P1 ; <float> [#uses=1]
|
||||||
;CHECK: vcvt.u32.f32
|
;CHECK: vcvt.u32.f32
|
||||||
%b1 = fptoui float %a1 to i32 ; <i32> [#uses=1]
|
%b1 = fptoui float %a1 to i32 ; <i32> [#uses=1]
|
||||||
@ -79,7 +79,7 @@ define i32 @test_ftou(float* %P1) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_dtoi(double* %P1) {
|
define i32 @test_dtoi(double* %P1) {
|
||||||
;CHECK: test_dtoi:
|
;CHECK-LABEL: test_dtoi:
|
||||||
%a1 = load double* %P1 ; <double> [#uses=1]
|
%a1 = load double* %P1 ; <double> [#uses=1]
|
||||||
;CHECK: vcvt.s32.f64
|
;CHECK: vcvt.s32.f64
|
||||||
%b1 = fptosi double %a1 to i32 ; <i32> [#uses=1]
|
%b1 = fptosi double %a1 to i32 ; <i32> [#uses=1]
|
||||||
@ -87,7 +87,7 @@ define i32 @test_dtoi(double* %P1) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define i32 @test_dtou(double* %P1) {
|
define i32 @test_dtou(double* %P1) {
|
||||||
;CHECK: test_dtou:
|
;CHECK-LABEL: test_dtou:
|
||||||
%a1 = load double* %P1 ; <double> [#uses=1]
|
%a1 = load double* %P1 ; <double> [#uses=1]
|
||||||
;CHECK: vcvt.u32.f64
|
;CHECK: vcvt.u32.f64
|
||||||
%b1 = fptoui double %a1 to i32 ; <i32> [#uses=1]
|
%b1 = fptoui double %a1 to i32 ; <i32> [#uses=1]
|
||||||
@ -95,7 +95,7 @@ define i32 @test_dtou(double* %P1) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_utod(double* %P1, i32 %X) {
|
define void @test_utod(double* %P1, i32 %X) {
|
||||||
;CHECK: test_utod:
|
;CHECK-LABEL: test_utod:
|
||||||
;CHECK: vcvt.f64.u32
|
;CHECK: vcvt.f64.u32
|
||||||
%b1 = uitofp i32 %X to double ; <double> [#uses=1]
|
%b1 = uitofp i32 %X to double ; <double> [#uses=1]
|
||||||
store double %b1, double* %P1
|
store double %b1, double* %P1
|
||||||
@ -103,7 +103,7 @@ define void @test_utod(double* %P1, i32 %X) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_utod2(double* %P1, i8 %X) {
|
define void @test_utod2(double* %P1, i8 %X) {
|
||||||
;CHECK: test_utod2:
|
;CHECK-LABEL: test_utod2:
|
||||||
;CHECK: vcvt.f64.u32
|
;CHECK: vcvt.f64.u32
|
||||||
%b1 = uitofp i8 %X to double ; <double> [#uses=1]
|
%b1 = uitofp i8 %X to double ; <double> [#uses=1]
|
||||||
store double %b1, double* %P1
|
store double %b1, double* %P1
|
||||||
@ -111,7 +111,7 @@ define void @test_utod2(double* %P1, i8 %X) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define void @test_cmp(float* %glob, i32 %X) {
|
define void @test_cmp(float* %glob, i32 %X) {
|
||||||
;CHECK: test_cmp:
|
;CHECK-LABEL: test_cmp:
|
||||||
entry:
|
entry:
|
||||||
%tmp = load float* %glob ; <float> [#uses=2]
|
%tmp = load float* %glob ; <float> [#uses=2]
|
||||||
%tmp3 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1]
|
%tmp3 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1]
|
||||||
@ -139,7 +139,7 @@ declare i32 @bar(...)
|
|||||||
declare i32 @baz(...)
|
declare i32 @baz(...)
|
||||||
|
|
||||||
define void @test_cmpfp0(float* %glob, i32 %X) {
|
define void @test_cmpfp0(float* %glob, i32 %X) {
|
||||||
;CHECK: test_cmpfp0:
|
;CHECK-LABEL: test_cmpfp0:
|
||||||
entry:
|
entry:
|
||||||
%tmp = load float* %glob ; <float> [#uses=1]
|
%tmp = load float* %glob ; <float> [#uses=1]
|
||||||
;CHECK: vcmpe.f32
|
;CHECK: vcmpe.f32
|
||||||
|
|||||||
@ -207,7 +207,7 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
|
define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
|
||||||
;CHECK: test_vset_lanef32:
|
;CHECK-LABEL: test_vset_lanef32:
|
||||||
;CHECK: vmov.f32 s3, s0
|
;CHECK: vmov.f32 s3, s0
|
||||||
;CHECK: vmov.f64 d0, d1
|
;CHECK: vmov.f64 d0, d1
|
||||||
entry:
|
entry:
|
||||||
|
|||||||
@ -95,7 +95,7 @@ declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind rea
|
|||||||
|
|
||||||
define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
|
define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test_vmul_lanef32:
|
; CHECK-LABEL: test_vmul_lanef32:
|
||||||
; CHECK: vmul.f32 d0, d0, d1[0]
|
; CHECK: vmul.f32 d0, d0, d1[0]
|
||||||
%0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]
|
%0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]
|
||||||
%1 = fmul <2 x float> %0, %arg0_float32x2_t ; <<2 x float>> [#uses=1]
|
%1 = fmul <2 x float> %0, %arg0_float32x2_t ; <<2 x float>> [#uses=1]
|
||||||
@ -104,7 +104,7 @@ entry:
|
|||||||
|
|
||||||
define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
|
define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test_vmul_lanes16:
|
; CHECK-LABEL: test_vmul_lanes16:
|
||||||
; CHECK: vmul.i16 d0, d0, d1[1]
|
; CHECK: vmul.i16 d0, d0, d1[1]
|
||||||
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$
|
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$
|
||||||
%1 = mul <4 x i16> %0, %arg0_int16x4_t ; <<4 x i16>> [#uses=1]
|
%1 = mul <4 x i16> %0, %arg0_int16x4_t ; <<4 x i16>> [#uses=1]
|
||||||
@ -113,7 +113,7 @@ entry:
|
|||||||
|
|
||||||
define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
|
define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test_vmul_lanes32:
|
; CHECK-LABEL: test_vmul_lanes32:
|
||||||
; CHECK: vmul.i32 d0, d0, d1[1]
|
; CHECK: vmul.i32 d0, d0, d1[1]
|
||||||
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
|
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
|
||||||
%1 = mul <2 x i32> %0, %arg0_int32x2_t ; <<2 x i32>> [#uses=1]
|
%1 = mul <2 x i32> %0, %arg0_int32x2_t ; <<2 x i32>> [#uses=1]
|
||||||
@ -122,7 +122,7 @@ entry:
|
|||||||
|
|
||||||
define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
|
define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test_vmulQ_lanef32:
|
; CHECK-LABEL: test_vmulQ_lanef32:
|
||||||
; CHECK: vmul.f32 q0, q0, d2[1]
|
; CHECK: vmul.f32 q0, q0, d2[1]
|
||||||
%0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$
|
%0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$
|
||||||
%1 = fmul <4 x float> %0, %arg0_float32x4_t ; <<4 x float>> [#uses=1]
|
%1 = fmul <4 x float> %0, %arg0_float32x4_t ; <<4 x float>> [#uses=1]
|
||||||
@ -131,7 +131,7 @@ entry:
|
|||||||
|
|
||||||
define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
|
define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test_vmulQ_lanes16:
|
; CHECK-LABEL: test_vmulQ_lanes16:
|
||||||
; CHECK: vmul.i16 q0, q0, d2[1]
|
; CHECK: vmul.i16 q0, q0, d2[1]
|
||||||
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
|
%0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
|
||||||
%1 = mul <8 x i16> %0, %arg0_int16x8_t ; <<8 x i16>> [#uses=1]
|
%1 = mul <8 x i16> %0, %arg0_int16x8_t ; <<8 x i16>> [#uses=1]
|
||||||
@ -140,7 +140,7 @@ entry:
|
|||||||
|
|
||||||
define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
|
define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test_vmulQ_lanes32:
|
; CHECK-LABEL: test_vmulQ_lanes32:
|
||||||
; CHECK: vmul.i32 q0, q0, d2[1]
|
; CHECK: vmul.i32 q0, q0, d2[1]
|
||||||
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$
|
%0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$
|
||||||
%1 = mul <4 x i32> %0, %arg0_int32x4_t ; <<4 x i32>> [#uses=1]
|
%1 = mul <4 x i32> %0, %arg0_int32x4_t ; <<4 x i32>> [#uses=1]
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
|
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
|
||||||
|
|
||||||
define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
|
define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
|
||||||
;CHECK: test_vrev64D8:
|
;CHECK-LABEL: test_vrev64D8:
|
||||||
;CHECK: vrev64.8
|
;CHECK: vrev64.8
|
||||||
%tmp1 = load <8 x i8>* %A
|
%tmp1 = load <8 x i8>* %A
|
||||||
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
||||||
@ -9,7 +9,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
|
define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
|
||||||
;CHECK: test_vrev64D16:
|
;CHECK-LABEL: test_vrev64D16:
|
||||||
;CHECK: vrev64.16
|
;CHECK: vrev64.16
|
||||||
%tmp1 = load <4 x i16>* %A
|
%tmp1 = load <4 x i16>* %A
|
||||||
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
|
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
|
||||||
@ -17,7 +17,7 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
|
define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
|
||||||
;CHECK: test_vrev64D32:
|
;CHECK-LABEL: test_vrev64D32:
|
||||||
;CHECK: vrev64.32
|
;CHECK: vrev64.32
|
||||||
%tmp1 = load <2 x i32>* %A
|
%tmp1 = load <2 x i32>* %A
|
||||||
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
|
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
|
||||||
@ -25,7 +25,7 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
|
define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
|
||||||
;CHECK: test_vrev64Df:
|
;CHECK-LABEL: test_vrev64Df:
|
||||||
;CHECK: vrev64.32
|
;CHECK: vrev64.32
|
||||||
%tmp1 = load <2 x float>* %A
|
%tmp1 = load <2 x float>* %A
|
||||||
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
|
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
|
||||||
@ -33,7 +33,7 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
|
define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
|
||||||
;CHECK: test_vrev64Q8:
|
;CHECK-LABEL: test_vrev64Q8:
|
||||||
;CHECK: vrev64.8
|
;CHECK: vrev64.8
|
||||||
%tmp1 = load <16 x i8>* %A
|
%tmp1 = load <16 x i8>* %A
|
||||||
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
|
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
|
||||||
@ -41,7 +41,7 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
|
define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
|
||||||
;CHECK: test_vrev64Q16:
|
;CHECK-LABEL: test_vrev64Q16:
|
||||||
;CHECK: vrev64.16
|
;CHECK: vrev64.16
|
||||||
%tmp1 = load <8 x i16>* %A
|
%tmp1 = load <8 x i16>* %A
|
||||||
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
|
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
|
||||||
@ -49,7 +49,7 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
|
define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
|
||||||
;CHECK: test_vrev64Q32:
|
;CHECK-LABEL: test_vrev64Q32:
|
||||||
;CHECK: vrev64.32
|
;CHECK: vrev64.32
|
||||||
%tmp1 = load <4 x i32>* %A
|
%tmp1 = load <4 x i32>* %A
|
||||||
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
||||||
@ -57,7 +57,7 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
|
define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
|
||||||
;CHECK: test_vrev64Qf:
|
;CHECK-LABEL: test_vrev64Qf:
|
||||||
;CHECK: vrev64.32
|
;CHECK: vrev64.32
|
||||||
%tmp1 = load <4 x float>* %A
|
%tmp1 = load <4 x float>* %A
|
||||||
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
||||||
@ -65,7 +65,7 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
|
define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
|
||||||
;CHECK: test_vrev32D8:
|
;CHECK-LABEL: test_vrev32D8:
|
||||||
;CHECK: vrev32.8
|
;CHECK: vrev32.8
|
||||||
%tmp1 = load <8 x i8>* %A
|
%tmp1 = load <8 x i8>* %A
|
||||||
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
|
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
|
||||||
@ -73,7 +73,7 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
|
define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
|
||||||
;CHECK: test_vrev32D16:
|
;CHECK-LABEL: test_vrev32D16:
|
||||||
;CHECK: vrev32.16
|
;CHECK: vrev32.16
|
||||||
%tmp1 = load <4 x i16>* %A
|
%tmp1 = load <4 x i16>* %A
|
||||||
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
||||||
@ -81,7 +81,7 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
|
define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
|
||||||
;CHECK: test_vrev32Q8:
|
;CHECK-LABEL: test_vrev32Q8:
|
||||||
;CHECK: vrev32.8
|
;CHECK: vrev32.8
|
||||||
%tmp1 = load <16 x i8>* %A
|
%tmp1 = load <16 x i8>* %A
|
||||||
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
|
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
|
||||||
@ -89,7 +89,7 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
|
define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
|
||||||
;CHECK: test_vrev32Q16:
|
;CHECK-LABEL: test_vrev32Q16:
|
||||||
;CHECK: vrev32.16
|
;CHECK: vrev32.16
|
||||||
%tmp1 = load <8 x i16>* %A
|
%tmp1 = load <8 x i16>* %A
|
||||||
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
|
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
|
||||||
@ -97,7 +97,7 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
|
define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
|
||||||
;CHECK: test_vrev16D8:
|
;CHECK-LABEL: test_vrev16D8:
|
||||||
;CHECK: vrev16.8
|
;CHECK: vrev16.8
|
||||||
%tmp1 = load <8 x i8>* %A
|
%tmp1 = load <8 x i8>* %A
|
||||||
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
|
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
|
||||||
@ -105,7 +105,7 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
|
define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
|
||||||
;CHECK: test_vrev16Q8:
|
;CHECK-LABEL: test_vrev16Q8:
|
||||||
;CHECK: vrev16.8
|
;CHECK: vrev16.8
|
||||||
%tmp1 = load <16 x i8>* %A
|
%tmp1 = load <16 x i8>* %A
|
||||||
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
|
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
|
||||||
@ -115,7 +115,7 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
|
|||||||
; Undef shuffle indices should not prevent matching to VREV:
|
; Undef shuffle indices should not prevent matching to VREV:
|
||||||
|
|
||||||
define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
|
define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
|
||||||
;CHECK: test_vrev64D8_undef:
|
;CHECK-LABEL: test_vrev64D8_undef:
|
||||||
;CHECK: vrev64.8
|
;CHECK: vrev64.8
|
||||||
%tmp1 = load <8 x i8>* %A
|
%tmp1 = load <8 x i8>* %A
|
||||||
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
|
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
|
||||||
@ -123,7 +123,7 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
|
|||||||
}
|
}
|
||||||
|
|
||||||
define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
|
define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
|
||||||
;CHECK: test_vrev32Q16_undef:
|
;CHECK-LABEL: test_vrev32Q16_undef:
|
||||||
;CHECK: vrev32.16
|
;CHECK: vrev32.16
|
||||||
%tmp1 = load <8 x i16>* %A
|
%tmp1 = load <8 x i16>* %A
|
||||||
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
|
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
|
||||||
@ -133,7 +133,7 @@ define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
|
|||||||
; A vcombine feeding a VREV should not obscure things. Radar 8597007.
|
; A vcombine feeding a VREV should not obscure things. Radar 8597007.
|
||||||
|
|
||||||
define void @test_with_vcombine(<4 x float>* %v) nounwind {
|
define void @test_with_vcombine(<4 x float>* %v) nounwind {
|
||||||
;CHECK: test_with_vcombine:
|
;CHECK-LABEL: test_with_vcombine:
|
||||||
;CHECK-NOT: vext
|
;CHECK-NOT: vext
|
||||||
;CHECK: vrev64.32
|
;CHECK: vrev64.32
|
||||||
%tmp1 = load <4 x float>* %v, align 16
|
%tmp1 = load <4 x float>* %v, align 16
|
||||||
@ -151,7 +151,7 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind {
|
|||||||
; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
|
; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
|
||||||
; to <2 x i16> when stored to memory.
|
; to <2 x i16> when stored to memory.
|
||||||
define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
|
define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
|
||||||
; CHECK: test_vrev64:
|
; CHECK-LABEL: test_vrev64:
|
||||||
; CHECK: vst1.32
|
; CHECK: vst1.32
|
||||||
entry:
|
entry:
|
||||||
%0 = bitcast <4 x i16>* %source to <8 x i16>*
|
%0 = bitcast <4 x i16>* %source to <8 x i16>*
|
||||||
|
|||||||
@ -31,4 +31,4 @@ entry:
|
|||||||
%tmp2122 = trunc i128 %tmp21 to i64
|
%tmp2122 = trunc i128 %tmp21 to i64
|
||||||
store i64 %tmp2122, i64* %RH
|
store i64 %tmp2122, i64* %RH
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -37,4 +37,4 @@ define i32 @main() {
|
|||||||
%ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
|
%ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
|
||||||
call i32 (i8*, ...)* @printf( i8* %lt_s, i16 %val1 )
|
call i32 (i8*, ...)* @printf( i8* %lt_s, i16 %val1 )
|
||||||
ret i32 0
|
ret i32 0
|
||||||
}
|
}
|
||||||
|
|||||||
@ -41,4 +41,4 @@ define i32 @main() {
|
|||||||
call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r )
|
call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r )
|
||||||
call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r )
|
call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r )
|
||||||
ret i32 0
|
ret i32 0
|
||||||
}
|
}
|
||||||
|
|||||||
@ -37,4 +37,4 @@ define i32 @main() {
|
|||||||
%ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
|
%ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
|
||||||
call i32 (i8*, ...)* @printf( i8* %lt_s, i8 %val1 )
|
call i32 (i8*, ...)* @printf( i8* %lt_s, i8 %val1 )
|
||||||
ret i32 0
|
ret i32 0
|
||||||
}
|
}
|
||||||
|
|||||||
@ -11,4 +11,4 @@ test_label:
|
|||||||
|
|
||||||
ret:
|
ret:
|
||||||
ret i32 -1
|
ret i32 -1
|
||||||
}
|
}
|
||||||
|
|||||||
@ -26,4 +26,4 @@ entry:
|
|||||||
%tmp2122 = trunc i128 %tmp21 to i64
|
%tmp2122 = trunc i128 %tmp21 to i64
|
||||||
store i64 %tmp2122, i64* %RH
|
store i64 %tmp2122, i64* %RH
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -22,4 +22,4 @@ define void @i65_ls() nounwind {
|
|||||||
%tmp = load i65* @i65_l
|
%tmp = load i65* @i65_l
|
||||||
store i65 %tmp, i65* @i65_s
|
store i65 %tmp, i65* @i65_s
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|||||||
@ -6,7 +6,7 @@ target triple = "msp430---elf"
|
|||||||
; Function Attrs: nounwind
|
; Function Attrs: nounwind
|
||||||
define i16 @test(i16 %i) #0 {
|
define i16 @test(i16 %i) #0 {
|
||||||
entry:
|
entry:
|
||||||
; CHECK: test:
|
; CHECK-LABEL: test:
|
||||||
%retval = alloca i16, align 2
|
%retval = alloca i16, align 2
|
||||||
%i.addr = alloca i16, align 2
|
%i.addr = alloca i16, align 2
|
||||||
store i16 %i, i16* %i.addr, align 2
|
store i16 %i, i16* %i.addr, align 2
|
||||||
|
|||||||
@ -28,4 +28,4 @@ entry:
|
|||||||
; 16: save $ra, $s0, $s1, 2040
|
; 16: save $ra, $s0, $s1, 2040
|
||||||
; 16: addiu $sp, -48 # 16 bit inst
|
; 16: addiu $sp, -48 # 16 bit inst
|
||||||
; 16: addiu $sp, 48 # 16 bit inst
|
; 16: addiu $sp, 48 # 16 bit inst
|
||||||
; 16: restore $ra, $s0, $s1, 2040
|
; 16: restore $ra, $s0, $s1, 2040
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc -march=mipsel < %s | FileCheck %s
|
; RUN: llc -march=mipsel < %s | FileCheck %s
|
||||||
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
|
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
|
||||||
|
|
||||||
; CHECK: test_blez:
|
; CHECK-LABEL: test_blez:
|
||||||
; CHECK: blez ${{[0-9]+}}, $BB
|
; CHECK: blez ${{[0-9]+}}, $BB
|
||||||
|
|
||||||
define void @test_blez(i32 %a) {
|
define void @test_blez(i32 %a) {
|
||||||
@ -19,7 +19,7 @@ if.end:
|
|||||||
|
|
||||||
declare void @foo1()
|
declare void @foo1()
|
||||||
|
|
||||||
; CHECK: test_bgez:
|
; CHECK-LABEL: test_bgez:
|
||||||
; CHECK: bgez ${{[0-9]+}}, $BB
|
; CHECK: bgez ${{[0-9]+}}, $BB
|
||||||
|
|
||||||
define void @test_bgez(i32 %a) {
|
define void @test_bgez(i32 %a) {
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1
|
; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1
|
||||||
; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
|
; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
|
||||||
|
|
||||||
; R1: test_lbux:
|
; R1-LABEL: test_lbux:
|
||||||
; R1: lbux ${{[0-9]+}}
|
; R1: lbux ${{[0-9]+}}
|
||||||
|
|
||||||
define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
|
define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
|
||||||
@ -11,7 +11,7 @@ entry:
|
|||||||
ret i8 %0
|
ret i8 %0
|
||||||
}
|
}
|
||||||
|
|
||||||
; R1: test_lhx:
|
; R1-LABEL: test_lhx:
|
||||||
; R1: lhx ${{[0-9]+}}
|
; R1: lhx ${{[0-9]+}}
|
||||||
|
|
||||||
define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
|
define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
|
||||||
@ -21,7 +21,7 @@ entry:
|
|||||||
ret i16 %0
|
ret i16 %0
|
||||||
}
|
}
|
||||||
|
|
||||||
; R1: test_lwx:
|
; R1-LABEL: test_lwx:
|
||||||
; R1: lwx ${{[0-9]+}}
|
; R1: lwx ${{[0-9]+}}
|
||||||
|
|
||||||
define i32 @test_lwx(i32* nocapture %b, i32 %i) {
|
define i32 @test_lwx(i32* nocapture %b, i32 %i) {
|
||||||
@ -31,7 +31,7 @@ entry:
|
|||||||
ret i32 %0
|
ret i32 %0
|
||||||
}
|
}
|
||||||
|
|
||||||
; R1: test_add_v2q15_:
|
; R1-LABEL: test_add_v2q15_:
|
||||||
; R1: addq.ph ${{[0-9]+}}
|
; R1: addq.ph ${{[0-9]+}}
|
||||||
|
|
||||||
define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
|
define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
|
||||||
@ -44,7 +44,7 @@ entry:
|
|||||||
ret { i32 } %.fca.0.insert
|
ret { i32 } %.fca.0.insert
|
||||||
}
|
}
|
||||||
|
|
||||||
; R1: test_sub_v2q15_:
|
; R1-LABEL: test_sub_v2q15_:
|
||||||
; R1: subq.ph ${{[0-9]+}}
|
; R1: subq.ph ${{[0-9]+}}
|
||||||
|
|
||||||
define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
|
define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
|
||||||
@ -57,11 +57,11 @@ entry:
|
|||||||
ret { i32 } %.fca.0.insert
|
ret { i32 } %.fca.0.insert
|
||||||
}
|
}
|
||||||
|
|
||||||
; R2: test_mul_v2q15_:
|
; R2-LABEL: test_mul_v2q15_:
|
||||||
; R2: mul.ph ${{[0-9]+}}
|
; R2: mul.ph ${{[0-9]+}}
|
||||||
|
|
||||||
; mul.ph is an R2 instruction. Check that multiply node gets expanded.
|
; mul.ph is an R2 instruction. Check that multiply node gets expanded.
|
||||||
; R1: test_mul_v2q15_:
|
; R1-LABEL: test_mul_v2q15_:
|
||||||
; R1: mul ${{[0-9]+}}
|
; R1: mul ${{[0-9]+}}
|
||||||
; R1: mul ${{[0-9]+}}
|
; R1: mul ${{[0-9]+}}
|
||||||
|
|
||||||
@ -75,7 +75,7 @@ entry:
|
|||||||
ret { i32 } %.fca.0.insert
|
ret { i32 } %.fca.0.insert
|
||||||
}
|
}
|
||||||
|
|
||||||
; R1: test_add_v4i8_:
|
; R1-LABEL: test_add_v4i8_:
|
||||||
; R1: addu.qb ${{[0-9]+}}
|
; R1: addu.qb ${{[0-9]+}}
|
||||||
|
|
||||||
define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
|
define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
|
||||||
@ -88,7 +88,7 @@ entry:
|
|||||||
ret { i32 } %.fca.0.insert
|
ret { i32 } %.fca.0.insert
|
||||||
}
|
}
|
||||||
|
|
||||||
; R1: test_sub_v4i8_:
|
; R1-LABEL: test_sub_v4i8_:
|
||||||
; R1: subu.qb ${{[0-9]+}}
|
; R1: subu.qb ${{[0-9]+}}
|
||||||
|
|
||||||
define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
|
define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
|
||||||
@ -102,7 +102,7 @@ entry:
|
|||||||
}
|
}
|
||||||
|
|
||||||
; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded.
|
; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded.
|
||||||
; R2: test_mul_v4i8_:
|
; R2-LABEL: test_mul_v4i8_:
|
||||||
; R2: mul ${{[0-9]+}}
|
; R2: mul ${{[0-9]+}}
|
||||||
; R2: mul ${{[0-9]+}}
|
; R2: mul ${{[0-9]+}}
|
||||||
; R2: mul ${{[0-9]+}}
|
; R2: mul ${{[0-9]+}}
|
||||||
@ -118,7 +118,7 @@ entry:
|
|||||||
ret { i32 } %.fca.0.insert
|
ret { i32 } %.fca.0.insert
|
||||||
}
|
}
|
||||||
|
|
||||||
; R1: test_addsc:
|
; R1-LABEL: test_addsc:
|
||||||
; R1: addsc ${{[0-9]+}}
|
; R1: addsc ${{[0-9]+}}
|
||||||
; R1: addwc ${{[0-9]+}}
|
; R1: addwc ${{[0-9]+}}
|
||||||
|
|
||||||
@ -206,7 +206,7 @@ entry:
|
|||||||
|
|
||||||
; Check that shift node is expanded if splat element size is not 16-bit.
|
; Check that shift node is expanded if splat element size is not 16-bit.
|
||||||
;
|
;
|
||||||
; R1: test_vector_splat_imm_v2q15:
|
; R1-LABEL: test_vector_splat_imm_v2q15:
|
||||||
; R1-NOT: shll.ph
|
; R1-NOT: shll.ph
|
||||||
|
|
||||||
define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) {
|
define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) {
|
||||||
@ -220,7 +220,7 @@ entry:
|
|||||||
|
|
||||||
; Check that shift node is expanded if splat element size is not 8-bit.
|
; Check that shift node is expanded if splat element size is not 8-bit.
|
||||||
;
|
;
|
||||||
; R1: test_vector_splat_imm_v4i8:
|
; R1-LABEL: test_vector_splat_imm_v4i8:
|
||||||
; R1-NOT: shll.qb
|
; R1-NOT: shll.qb
|
||||||
|
|
||||||
define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) {
|
define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) {
|
||||||
@ -234,7 +234,7 @@ entry:
|
|||||||
|
|
||||||
; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field.
|
; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field.
|
||||||
;
|
;
|
||||||
; R1: test_shift_amount_v2q15:
|
; R1-LABEL: test_shift_amount_v2q15:
|
||||||
; R1-NOT: shll.ph
|
; R1-NOT: shll.ph
|
||||||
|
|
||||||
define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) {
|
define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) {
|
||||||
@ -248,7 +248,7 @@ entry:
|
|||||||
|
|
||||||
; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field.
|
; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field.
|
||||||
;
|
;
|
||||||
; R1: test_shift_amount_v4i8:
|
; R1-LABEL: test_shift_amount_v4i8:
|
||||||
; R1-NOT: shll.qb
|
; R1-NOT: shll.qb
|
||||||
|
|
||||||
define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) {
|
define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) {
|
||||||
|
|||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user