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Add the remaining AVX versions of instructions to X86InstrInfo, this
time for describing high latency ones and for recognizting loads from the same base pointer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139864 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3112,13 +3112,16 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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case X86::MMX_MOVQ64rm:
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case X86::FsMOVAPSrm:
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case X86::FsMOVAPDrm:
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case X86::FsVMOVAPSrm:
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case X86::FsVMOVAPDrm:
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case X86::MOVAPSrm:
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case X86::MOVUPSrm:
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case X86::MOVAPDrm:
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case X86::MOVDQArm:
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case X86::MOVDQUrm:
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// AVX load instructions
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case X86::VMOVSSrm:
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case X86::VMOVSDrm:
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case X86::FsVMOVAPSrm:
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case X86::FsVMOVAPDrm:
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case X86::VMOVAPSrm:
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case X86::VMOVUPSrm:
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case X86::VMOVAPDrm:
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@ -3146,13 +3149,16 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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case X86::MMX_MOVQ64rm:
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case X86::FsMOVAPSrm:
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case X86::FsMOVAPDrm:
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case X86::FsVMOVAPSrm:
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case X86::FsVMOVAPDrm:
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case X86::MOVAPSrm:
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case X86::MOVUPSrm:
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case X86::MOVAPDrm:
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case X86::MOVDQArm:
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case X86::MOVDQUrm:
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// AVX load instructions
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case X86::VMOVSSrm:
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case X86::VMOVSDrm:
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case X86::FsVMOVAPSrm:
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case X86::FsVMOVAPDrm:
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case X86::VMOVAPSrm:
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case X86::VMOVUPSrm:
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case X86::VMOVAPDrm:
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@ -3383,6 +3389,29 @@ bool X86InstrInfo::isHighLatencyDef(int opc) const {
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case X86::SQRTSSm_Int:
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case X86::SQRTSSr:
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case X86::SQRTSSr_Int:
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// AVX instructions with high latency
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case X86::VDIVSDrm:
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case X86::VDIVSDrm_Int:
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case X86::VDIVSDrr:
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case X86::VDIVSDrr_Int:
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case X86::VDIVSSrm:
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case X86::VDIVSSrm_Int:
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case X86::VDIVSSrr:
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case X86::VDIVSSrr_Int:
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case X86::VSQRTPDm:
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case X86::VSQRTPDm_Int:
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case X86::VSQRTPDr:
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case X86::VSQRTPDr_Int:
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case X86::VSQRTPSm:
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case X86::VSQRTPSm_Int:
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case X86::VSQRTPSr:
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case X86::VSQRTPSr_Int:
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case X86::VSQRTSDm:
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case X86::VSQRTSDm_Int:
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case X86::VSQRTSDr:
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case X86::VSQRTSSm:
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case X86::VSQRTSSm_Int:
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case X86::VSQRTSSr:
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return true;
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}
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}
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