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[SystemZ] Add CodeGen test cases

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This adds all CodeGen tests for the SystemZ target.

This version of the patch incorporates feedback from a review by
Sean Silva.  Thanks to all reviewers!

Patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
2013-05-06 16:17:29 +00:00
parent 1d09d56fe1
commit b503b49b51
296 changed files with 31125 additions and 0 deletions
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107
test/CodeGen/SystemZ/int-cmp-04.ll Normal file
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; Test 64-bit signed comparison in which the second operand is sign-extended
; from an i16 memory value.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; Check CGH with no displacement.
define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
; CHECK: f1:
; CHECK: cgh %r2, 0(%r3)
; CHECK: br %r14
%half = load i16 *%src
%rhs = sext i16 %half to i64
%cond = icmp slt i64 %lhs, %rhs
%res = select i1 %cond, i64 100, i64 200
store i64 %res, i64 *%dst
ret void
}
; Check the high end of the aligned CGH range.
define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
; CHECK: f2:
; CHECK: cgh %r2, 524286(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
%half = load i16 *%ptr
%rhs = sext i16 %half to i64
%cond = icmp slt i64 %lhs, %rhs
%res = select i1 %cond, i64 100, i64 200
store i64 %res, i64 *%dst
ret void
}
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
; CHECK: f3:
; CHECK: agfi %r3, 524288
; CHECK: cgh %r2, 0(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262144
%half = load i16 *%ptr
%rhs = sext i16 %half to i64
%cond = icmp slt i64 %lhs, %rhs
%res = select i1 %cond, i64 100, i64 200
store i64 %res, i64 *%dst
ret void
}
; Check the high end of the negative aligned CGH range.
define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
; CHECK: f4:
; CHECK: cgh %r2, -2(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
%half = load i16 *%ptr
%rhs = sext i16 %half to i64
%cond = icmp slt i64 %lhs, %rhs
%res = select i1 %cond, i64 100, i64 200
store i64 %res, i64 *%dst
ret void
}
; Check the low end of the CGH range.
define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
; CHECK: f5:
; CHECK: cgh %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
%half = load i16 *%ptr
%rhs = sext i16 %half to i64
%cond = icmp slt i64 %lhs, %rhs
%res = select i1 %cond, i64 100, i64 200
store i64 %res, i64 *%dst
ret void
}
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
; CHECK: f6:
; CHECK: agfi %r3, -524290
; CHECK: cgh %r2, 0(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262145
%half = load i16 *%ptr
%rhs = sext i16 %half to i64
%cond = icmp slt i64 %lhs, %rhs
%res = select i1 %cond, i64 100, i64 200
store i64 %res, i64 *%dst
ret void
}
; Check that CGH allows an index.
define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) {
; CHECK: f7:
; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %base, %index
%add2 = add i64 %add1, 4096
%ptr = inttoptr i64 %add2 to i16 *
%half = load i16 *%ptr
%rhs = sext i16 %half to i64
%cond = icmp slt i64 %lhs, %rhs
%res = select i1 %cond, i64 100, i64 200
store i64 %res, i64 *%dst
ret void
}