mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-06 21:29:27 +00:00
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74731 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -47,91 +47,6 @@ ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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}
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
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SrcSubIdx = DstSubIdx = 0; // No sub-registers.
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unsigned oc = MI.getOpcode();
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switch (oc) {
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default:
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return false;
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case ARM::FCPYS:
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case ARM::FCPYD:
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case ARM::VMOVD:
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case ARM::VMOVQ:
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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case ARM::MOVr:
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assert(MI.getDesc().getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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"Invalid ARM MOV instruction");
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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}
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unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case ARM::LDR:
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if (MI->getOperand(1).isFI() &&
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MI->getOperand(2).isReg() &&
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MI->getOperand(3).isImm() &&
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MI->getOperand(2).getReg() == 0 &&
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MI->getOperand(3).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::FLDD:
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case ARM::FLDS:
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if (MI->getOperand(1).isFI() &&
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MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case ARM::STR:
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if (MI->getOperand(1).isFI() &&
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MI->getOperand(2).isReg() &&
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MI->getOperand(3).isImm() &&
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MI->getOperand(2).getReg() == 0 &&
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MI->getOperand(3).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::FSTD:
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case ARM::FSTS:
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if (MI->getOperand(1).isFI() &&
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MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
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void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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unsigned DestReg,
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@ -335,10 +250,10 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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// Branch analysis.
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// Branch analysis.
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bool
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bool
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ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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bool AllowModify) const {
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// If the block has no terminators, it just falls into the block after it.
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
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@ -478,239 +393,6 @@ ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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return 2;
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return 2;
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}
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}
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bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC != SrcRC) {
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// Not yet supported!
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return false;
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}
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if (DestRC == ARM::GPRRegisterClass)
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
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.addReg(SrcReg)));
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else if (DestRC == ARM::SPRRegisterClass)
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
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.addReg(SrcReg));
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else if (DestRC == ARM::DPRRegisterClass)
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
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.addReg(SrcReg));
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else if (DestRC == ARM::QPRRegisterClass)
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BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
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else
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return false;
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return true;
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}
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void ARMInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == ARM::GPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addReg(0).addImm(0));
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} else if (RC == ARM::DPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0));
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} else {
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assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0));
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}
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}
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void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const{
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DebugLoc DL = DebugLoc::getUnknownLoc();
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unsigned Opc = 0;
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if (RC == ARM::GPRRegisterClass) {
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Opc = ARM::STR;
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} else if (RC == ARM::DPRRegisterClass) {
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Opc = ARM::FSTD;
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} else {
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assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
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Opc = ARM::FSTS;
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}
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MachineInstrBuilder MIB =
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BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
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for (unsigned i = 0, e = Addr.size(); i != e; ++i)
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MIB.addOperand(Addr[i]);
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AddDefaultPred(MIB);
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NewMIs.push_back(MIB);
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return;
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}
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void ARMInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == ARM::GPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
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.addFrameIndex(FI).addReg(0).addImm(0));
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} else if (RC == ARM::DPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
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.addFrameIndex(FI).addImm(0));
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} else {
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assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
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.addFrameIndex(FI).addImm(0));
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}
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}
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void ARMInstrInfo::
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loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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unsigned Opc = 0;
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if (RC == ARM::GPRRegisterClass) {
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Opc = ARM::LDR;
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} else if (RC == ARM::DPRRegisterClass) {
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Opc = ARM::FLDD;
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} else {
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assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
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Opc = ARM::FLDS;
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}
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i)
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MIB.addOperand(Addr[i]);
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AddDefaultPred(MIB);
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NewMIs.push_back(MIB);
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return;
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}
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MachineInstr *ARMInstrInfo::
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops, int FI) const {
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if (Ops.size() != 1) return NULL;
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unsigned OpNum = Ops[0];
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unsigned Opc = MI->getOpcode();
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MachineInstr *NewMI = NULL;
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switch (Opc) {
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default: break;
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case ARM::MOVr: {
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if (MI->getOperand(4).getReg() == ARM::CPSR)
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// If it is updating CPSR, then it cannot be folded.
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break;
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unsigned Pred = MI->getOperand(2).getImm();
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unsigned PredReg = MI->getOperand(3).getReg();
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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bool isUndef = MI->getOperand(1).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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bool isDead = MI->getOperand(0).isDead();
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bool isUndef = MI->getOperand(0).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
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.addReg(DstReg,
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RegState::Define |
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getDeadRegState(isDead) |
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getUndefRegState(isUndef))
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.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
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}
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break;
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}
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case ARM::FCPYS: {
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unsigned Pred = MI->getOperand(2).getImm();
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unsigned PredReg = MI->getOperand(3).getReg();
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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bool isUndef = MI->getOperand(1).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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.addFrameIndex(FI)
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.addImm(0).addImm(Pred).addReg(PredReg);
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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bool isDead = MI->getOperand(0).isDead();
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bool isUndef = MI->getOperand(0).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
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.addReg(DstReg,
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RegState::Define |
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getDeadRegState(isDead) |
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getUndefRegState(isUndef))
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.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
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}
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break;
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}
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case ARM::FCPYD: {
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unsigned Pred = MI->getOperand(2).getImm();
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unsigned PredReg = MI->getOperand(3).getReg();
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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bool isUndef = MI->getOperand(1).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
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.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
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.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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bool isDead = MI->getOperand(0).isDead();
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bool isUndef = MI->getOperand(0).isUndef();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
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.addReg(DstReg,
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RegState::Define |
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getDeadRegState(isDead) |
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getUndefRegState(isUndef))
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.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
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}
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break;
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}
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}
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return NewMI;
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}
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bool
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ARMInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const {
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if (Ops.size() != 1) return false;
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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default: break;
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case ARM::MOVr:
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// If it is updating CPSR, then it cannot be folded.
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return MI->getOperand(4).getReg() != ARM::CPSR;
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case ARM::FCPYS:
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case ARM::FCPYD:
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return true;
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case ARM::VMOVD:
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case ARM::VMOVQ:
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return false; // FIXME
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}
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return false;
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}
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bool
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bool
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ARMBaseInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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ARMBaseInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
|
if (MBB.empty()) return false;
|
||||||
@ -898,3 +580,334 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
|
|||||||
}
|
}
|
||||||
return 0; // Not reached
|
return 0; // Not reached
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/// Return true if the instruction is a register to register move and
|
||||||
|
/// leave the source and dest operands in the passed parameters.
|
||||||
|
///
|
||||||
|
bool
|
||||||
|
ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
|
||||||
|
unsigned &SrcReg, unsigned &DstReg,
|
||||||
|
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
|
||||||
|
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
|
||||||
|
|
||||||
|
unsigned oc = MI.getOpcode();
|
||||||
|
switch (oc) {
|
||||||
|
default:
|
||||||
|
return false;
|
||||||
|
case ARM::FCPYS:
|
||||||
|
case ARM::FCPYD:
|
||||||
|
case ARM::VMOVD:
|
||||||
|
case ARM::VMOVQ:
|
||||||
|
SrcReg = MI.getOperand(1).getReg();
|
||||||
|
DstReg = MI.getOperand(0).getReg();
|
||||||
|
return true;
|
||||||
|
case ARM::MOVr:
|
||||||
|
assert(MI.getDesc().getNumOperands() >= 2 &&
|
||||||
|
MI.getOperand(0).isReg() &&
|
||||||
|
MI.getOperand(1).isReg() &&
|
||||||
|
"Invalid ARM MOV instruction");
|
||||||
|
SrcReg = MI.getOperand(1).getReg();
|
||||||
|
DstReg = MI.getOperand(0).getReg();
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned
|
||||||
|
ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
||||||
|
int &FrameIndex) const {
|
||||||
|
switch (MI->getOpcode()) {
|
||||||
|
default: break;
|
||||||
|
case ARM::LDR:
|
||||||
|
if (MI->getOperand(1).isFI() &&
|
||||||
|
MI->getOperand(2).isReg() &&
|
||||||
|
MI->getOperand(3).isImm() &&
|
||||||
|
MI->getOperand(2).getReg() == 0 &&
|
||||||
|
MI->getOperand(3).getImm() == 0) {
|
||||||
|
FrameIndex = MI->getOperand(1).getIndex();
|
||||||
|
return MI->getOperand(0).getReg();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case ARM::FLDD:
|
||||||
|
case ARM::FLDS:
|
||||||
|
if (MI->getOperand(1).isFI() &&
|
||||||
|
MI->getOperand(2).isImm() &&
|
||||||
|
MI->getOperand(2).getImm() == 0) {
|
||||||
|
FrameIndex = MI->getOperand(1).getIndex();
|
||||||
|
return MI->getOperand(0).getReg();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned
|
||||||
|
ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
|
||||||
|
int &FrameIndex) const {
|
||||||
|
switch (MI->getOpcode()) {
|
||||||
|
default: break;
|
||||||
|
case ARM::STR:
|
||||||
|
if (MI->getOperand(1).isFI() &&
|
||||||
|
MI->getOperand(2).isReg() &&
|
||||||
|
MI->getOperand(3).isImm() &&
|
||||||
|
MI->getOperand(2).getReg() == 0 &&
|
||||||
|
MI->getOperand(3).getImm() == 0) {
|
||||||
|
FrameIndex = MI->getOperand(1).getIndex();
|
||||||
|
return MI->getOperand(0).getReg();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case ARM::FSTD:
|
||||||
|
case ARM::FSTS:
|
||||||
|
if (MI->getOperand(1).isFI() &&
|
||||||
|
MI->getOperand(2).isImm() &&
|
||||||
|
MI->getOperand(2).getImm() == 0) {
|
||||||
|
FrameIndex = MI->getOperand(1).getIndex();
|
||||||
|
return MI->getOperand(0).getReg();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool
|
||||||
|
ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator I,
|
||||||
|
unsigned DestReg, unsigned SrcReg,
|
||||||
|
const TargetRegisterClass *DestRC,
|
||||||
|
const TargetRegisterClass *SrcRC) const {
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||||
|
|
||||||
|
if (DestRC != SrcRC) {
|
||||||
|
// Not yet supported!
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (DestRC == ARM::GPRRegisterClass)
|
||||||
|
AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
|
||||||
|
.addReg(SrcReg)));
|
||||||
|
else if (DestRC == ARM::SPRRegisterClass)
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
|
||||||
|
.addReg(SrcReg));
|
||||||
|
else if (DestRC == ARM::DPRRegisterClass)
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
|
||||||
|
.addReg(SrcReg));
|
||||||
|
else if (DestRC == ARM::QPRRegisterClass)
|
||||||
|
BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
|
||||||
|
else
|
||||||
|
return false;
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
void ARMBaseInstrInfo::
|
||||||
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned SrcReg, bool isKill, int FI,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||||
|
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
|
||||||
|
.addReg(SrcReg, getKillRegState(isKill))
|
||||||
|
.addFrameIndex(FI).addReg(0).addImm(0));
|
||||||
|
} else if (RC == ARM::DPRRegisterClass) {
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
|
||||||
|
.addReg(SrcReg, getKillRegState(isKill))
|
||||||
|
.addFrameIndex(FI).addImm(0));
|
||||||
|
} else {
|
||||||
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
|
||||||
|
.addReg(SrcReg, getKillRegState(isKill))
|
||||||
|
.addFrameIndex(FI).addImm(0));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
ARMBaseInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
Opc = ARM::STR;
|
||||||
|
} else if (RC == ARM::DPRRegisterClass) {
|
||||||
|
Opc = ARM::FSTD;
|
||||||
|
} else {
|
||||||
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
||||||
|
Opc = ARM::FSTS;
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstrBuilder MIB =
|
||||||
|
BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB.addOperand(Addr[i]);
|
||||||
|
AddDefaultPred(MIB);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
void ARMBaseInstrInfo::
|
||||||
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned DestReg, int FI,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||||
|
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
|
||||||
|
.addFrameIndex(FI).addReg(0).addImm(0));
|
||||||
|
} else if (RC == ARM::DPRRegisterClass) {
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
|
||||||
|
.addFrameIndex(FI).addImm(0));
|
||||||
|
} else {
|
||||||
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
|
||||||
|
.addFrameIndex(FI).addImm(0));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void ARMBaseInstrInfo::
|
||||||
|
loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
Opc = ARM::LDR;
|
||||||
|
} else if (RC == ARM::DPRRegisterClass) {
|
||||||
|
Opc = ARM::FLDD;
|
||||||
|
} else {
|
||||||
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
||||||
|
Opc = ARM::FLDS;
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB.addOperand(Addr[i]);
|
||||||
|
AddDefaultPred(MIB);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstr *ARMBaseInstrInfo::
|
||||||
|
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
|
||||||
|
const SmallVectorImpl<unsigned> &Ops, int FI) const {
|
||||||
|
if (Ops.size() != 1) return NULL;
|
||||||
|
|
||||||
|
unsigned OpNum = Ops[0];
|
||||||
|
unsigned Opc = MI->getOpcode();
|
||||||
|
MachineInstr *NewMI = NULL;
|
||||||
|
switch (Opc) {
|
||||||
|
default: break;
|
||||||
|
case ARM::MOVr: {
|
||||||
|
if (MI->getOperand(4).getReg() == ARM::CPSR)
|
||||||
|
// If it is updating CPSR, then it cannot be folded.
|
||||||
|
break;
|
||||||
|
unsigned Pred = MI->getOperand(2).getImm();
|
||||||
|
unsigned PredReg = MI->getOperand(3).getReg();
|
||||||
|
if (OpNum == 0) { // move -> store
|
||||||
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
||||||
|
bool isKill = MI->getOperand(1).isKill();
|
||||||
|
bool isUndef = MI->getOperand(1).isUndef();
|
||||||
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
|
||||||
|
.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
|
||||||
|
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
|
||||||
|
} else { // move -> load
|
||||||
|
unsigned DstReg = MI->getOperand(0).getReg();
|
||||||
|
bool isDead = MI->getOperand(0).isDead();
|
||||||
|
bool isUndef = MI->getOperand(0).isUndef();
|
||||||
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
|
||||||
|
.addReg(DstReg,
|
||||||
|
RegState::Define |
|
||||||
|
getDeadRegState(isDead) |
|
||||||
|
getUndefRegState(isUndef))
|
||||||
|
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case ARM::FCPYS: {
|
||||||
|
unsigned Pred = MI->getOperand(2).getImm();
|
||||||
|
unsigned PredReg = MI->getOperand(3).getReg();
|
||||||
|
if (OpNum == 0) { // move -> store
|
||||||
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
||||||
|
bool isKill = MI->getOperand(1).isKill();
|
||||||
|
bool isUndef = MI->getOperand(1).isUndef();
|
||||||
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
|
||||||
|
.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
|
||||||
|
.addFrameIndex(FI)
|
||||||
|
.addImm(0).addImm(Pred).addReg(PredReg);
|
||||||
|
} else { // move -> load
|
||||||
|
unsigned DstReg = MI->getOperand(0).getReg();
|
||||||
|
bool isDead = MI->getOperand(0).isDead();
|
||||||
|
bool isUndef = MI->getOperand(0).isUndef();
|
||||||
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
|
||||||
|
.addReg(DstReg,
|
||||||
|
RegState::Define |
|
||||||
|
getDeadRegState(isDead) |
|
||||||
|
getUndefRegState(isUndef))
|
||||||
|
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case ARM::FCPYD: {
|
||||||
|
unsigned Pred = MI->getOperand(2).getImm();
|
||||||
|
unsigned PredReg = MI->getOperand(3).getReg();
|
||||||
|
if (OpNum == 0) { // move -> store
|
||||||
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
||||||
|
bool isKill = MI->getOperand(1).isKill();
|
||||||
|
bool isUndef = MI->getOperand(1).isUndef();
|
||||||
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
|
||||||
|
.addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
|
||||||
|
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
|
||||||
|
} else { // move -> load
|
||||||
|
unsigned DstReg = MI->getOperand(0).getReg();
|
||||||
|
bool isDead = MI->getOperand(0).isDead();
|
||||||
|
bool isUndef = MI->getOperand(0).isUndef();
|
||||||
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
|
||||||
|
.addReg(DstReg,
|
||||||
|
RegState::Define |
|
||||||
|
getDeadRegState(isDead) |
|
||||||
|
getUndefRegState(isUndef))
|
||||||
|
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return NewMI;
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstr*
|
||||||
|
ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
|
||||||
|
MachineInstr* MI,
|
||||||
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
|
MachineInstr* LoadMI) const {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool
|
||||||
|
ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
|
||||||
|
const SmallVectorImpl<unsigned> &Ops) const {
|
||||||
|
if (Ops.size() != 1) return false;
|
||||||
|
|
||||||
|
unsigned Opc = MI->getOpcode();
|
||||||
|
switch (Opc) {
|
||||||
|
default: break;
|
||||||
|
case ARM::MOVr:
|
||||||
|
// If it is updating CPSR, then it cannot be folded.
|
||||||
|
return MI->getOperand(4).getReg() != ARM::CPSR;
|
||||||
|
case ARM::FCPYS:
|
||||||
|
case ARM::FCPYD:
|
||||||
|
return true;
|
||||||
|
|
||||||
|
case ARM::VMOVD:
|
||||||
|
case ARM::VMOVQ:
|
||||||
|
return false; // FIXME
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
@ -161,6 +161,8 @@ public:
|
|||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
LiveVariables *LV) const;
|
LiveVariables *LV) const;
|
||||||
|
|
||||||
|
virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
|
||||||
|
|
||||||
// Branch analysis.
|
// Branch analysis.
|
||||||
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
||||||
MachineBasicBlock *&FBB,
|
MachineBasicBlock *&FBB,
|
||||||
@ -198,18 +200,6 @@ public:
|
|||||||
/// GetInstSize - Returns the size of the specified MachineInstr.
|
/// GetInstSize - Returns the size of the specified MachineInstr.
|
||||||
///
|
///
|
||||||
virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
|
virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
|
||||||
};
|
|
||||||
|
|
||||||
class ARMInstrInfo : public ARMBaseInstrInfo {
|
|
||||||
ARMRegisterInfo RI;
|
|
||||||
public:
|
|
||||||
explicit ARMInstrInfo(const ARMSubtarget &STI);
|
|
||||||
|
|
||||||
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
|
||||||
/// such, whenever a client has an instance of instruction info, it should
|
|
||||||
/// always be able to get register info as well (through this method).
|
|
||||||
///
|
|
||||||
virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
|
|
||||||
|
|
||||||
/// Return true if the instruction is a register to register move and return
|
/// Return true if the instruction is a register to register move and return
|
||||||
/// the source and dest operands and their sub-register indices by reference.
|
/// the source and dest operands and their sub-register indices by reference.
|
||||||
@ -247,23 +237,33 @@ public:
|
|||||||
const TargetRegisterClass *RC,
|
const TargetRegisterClass *RC,
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, const MachineInstr *Orig) const;
|
|
||||||
|
|
||||||
virtual bool canFoldMemoryOperand(const MachineInstr *MI,
|
virtual bool canFoldMemoryOperand(const MachineInstr *MI,
|
||||||
const SmallVectorImpl<unsigned> &Ops) const;
|
const SmallVectorImpl<unsigned> &Ops) const;
|
||||||
|
|
||||||
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
||||||
MachineInstr* MI,
|
MachineInstr* MI,
|
||||||
const SmallVectorImpl<unsigned> &Ops,
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
int FrameIndex) const;
|
int FrameIndex) const;
|
||||||
|
|
||||||
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
||||||
MachineInstr* MI,
|
MachineInstr* MI,
|
||||||
const SmallVectorImpl<unsigned> &Ops,
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
MachineInstr* LoadMI) const {
|
MachineInstr* LoadMI) const;
|
||||||
return 0;
|
};
|
||||||
}
|
|
||||||
|
class ARMInstrInfo : public ARMBaseInstrInfo {
|
||||||
|
ARMRegisterInfo RI;
|
||||||
|
public:
|
||||||
|
explicit ARMInstrInfo(const ARMSubtarget &STI);
|
||||||
|
|
||||||
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
||||||
|
/// such, whenever a client has an instance of instruction info, it should
|
||||||
|
/// always be able to get register info as well (through this method).
|
||||||
|
///
|
||||||
|
const ARMRegisterInfo &getRegisterInfo() const { return RI; }
|
||||||
|
|
||||||
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
|
unsigned DestReg, const MachineInstr *Orig) const;
|
||||||
};
|
};
|
||||||
|
|
||||||
}
|
}
|
||||||
|
@ -95,13 +95,18 @@ ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS)
|
|||||||
}
|
}
|
||||||
|
|
||||||
ThumbTargetMachine::ThumbTargetMachine(const Module &M, const std::string &FS)
|
ThumbTargetMachine::ThumbTargetMachine(const Module &M, const std::string &FS)
|
||||||
: ARMBaseTargetMachine(M, FS, true), InstrInfo(Subtarget),
|
: ARMBaseTargetMachine(M, FS, true),
|
||||||
DataLayout(Subtarget.isAPCS_ABI() ?
|
DataLayout(Subtarget.isAPCS_ABI() ?
|
||||||
std::string("e-p:32:32-f64:32:32-i64:32:32-"
|
std::string("e-p:32:32-f64:32:32-i64:32:32-"
|
||||||
"i16:16:32-i8:8:32-i1:8:32-a:0:32") :
|
"i16:16:32-i8:8:32-i1:8:32-a:0:32") :
|
||||||
std::string("e-p:32:32-f64:64:64-i64:64:64-"
|
std::string("e-p:32:32-f64:64:64-i64:64:64-"
|
||||||
"i16:16:32-i8:8:32-i1:8:32-a:0:32")),
|
"i16:16:32-i8:8:32-i1:8:32-a:0:32")),
|
||||||
TLInfo(*this) {
|
TLInfo(*this) {
|
||||||
|
// Create the approriate type of Thumb InstrInfo
|
||||||
|
if (Subtarget.hasThumb2())
|
||||||
|
InstrInfo = new Thumb2InstrInfo(Subtarget);
|
||||||
|
else
|
||||||
|
InstrInfo = new Thumb1InstrInfo(Subtarget);
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned ARMTargetMachine::getJITMatchQuality() {
|
unsigned ARMTargetMachine::getJITMatchQuality() {
|
||||||
|
@ -22,7 +22,8 @@
|
|||||||
#include "ARMJITInfo.h"
|
#include "ARMJITInfo.h"
|
||||||
#include "ARMSubtarget.h"
|
#include "ARMSubtarget.h"
|
||||||
#include "ARMISelLowering.h"
|
#include "ARMISelLowering.h"
|
||||||
#include "ThumbInstrInfo.h"
|
#include "Thumb1InstrInfo.h"
|
||||||
|
#include "Thumb2InstrInfo.h"
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
|
|
||||||
@ -111,23 +112,27 @@ public:
|
|||||||
};
|
};
|
||||||
|
|
||||||
/// ThumbTargetMachine - Thumb target machine.
|
/// ThumbTargetMachine - Thumb target machine.
|
||||||
|
/// Due to the way architectures are handled, this represents both
|
||||||
|
/// Thumb-1 and Thumb-2.
|
||||||
///
|
///
|
||||||
class ThumbTargetMachine : public ARMBaseTargetMachine {
|
class ThumbTargetMachine : public ARMBaseTargetMachine {
|
||||||
ThumbInstrInfo InstrInfo;
|
ARMBaseInstrInfo *InstrInfo; // either Thumb1InstrInfo or Thumb2InstrInfo
|
||||||
const TargetData DataLayout; // Calculates type size & alignment
|
const TargetData DataLayout; // Calculates type size & alignment
|
||||||
ARMTargetLowering TLInfo;
|
ARMTargetLowering TLInfo;
|
||||||
public:
|
public:
|
||||||
ThumbTargetMachine(const Module &M, const std::string &FS);
|
ThumbTargetMachine(const Module &M, const std::string &FS);
|
||||||
|
|
||||||
virtual const ThumbRegisterInfo *getRegisterInfo() const {
|
/// returns either Thumb1RegisterInfo of Thumb2RegisterInfo
|
||||||
return &InstrInfo.getRegisterInfo();
|
virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
|
||||||
|
return &InstrInfo->getRegisterInfo();
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual ARMTargetLowering *getTargetLowering() const {
|
virtual ARMTargetLowering *getTargetLowering() const {
|
||||||
return const_cast<ARMTargetLowering*>(&TLInfo);
|
return const_cast<ARMTargetLowering*>(&TLInfo);
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual const ThumbInstrInfo *getInstrInfo() const { return &InstrInfo; }
|
/// returns either Thumb1InstrInfo or Thumb2InstrInfo
|
||||||
|
virtual const ARMBaseInstrInfo *getInstrInfo() const { return InstrInfo; }
|
||||||
virtual const TargetData *getTargetData() const { return &DataLayout; }
|
virtual const TargetData *getTargetData() const { return &DataLayout; }
|
||||||
|
|
||||||
static unsigned getJITMatchQuality();
|
static unsigned getJITMatchQuality();
|
||||||
|
@ -24,8 +24,10 @@ add_llvm_target(ARMCodeGen
|
|||||||
ARMSubtarget.cpp
|
ARMSubtarget.cpp
|
||||||
ARMTargetAsmInfo.cpp
|
ARMTargetAsmInfo.cpp
|
||||||
ARMTargetMachine.cpp
|
ARMTargetMachine.cpp
|
||||||
ThumbInstrInfo.cpp
|
Thumb1InstrInfo.cpp
|
||||||
ThumbRegisterInfo.cpp
|
Thumb1RegisterInfo.cpp
|
||||||
|
Thumb2InstrInfo.cpp
|
||||||
|
Thumb2RegisterInfo.cpp
|
||||||
)
|
)
|
||||||
|
|
||||||
target_link_libraries (LLVMARMCodeGen LLVMSelectionDAG)
|
target_link_libraries (LLVMARMCodeGen LLVMSelectionDAG)
|
||||||
|
304
lib/Target/ARM/Thumb1InstrInfo.cpp
Normal file
304
lib/Target/ARM/Thumb1InstrInfo.cpp
Normal file
@ -0,0 +1,304 @@
|
|||||||
|
//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
|
||||||
|
//
|
||||||
|
// The LLVM Compiler Infrastructure
|
||||||
|
//
|
||||||
|
// This file is distributed under the University of Illinois Open Source
|
||||||
|
// License. See LICENSE.TXT for details.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
//
|
||||||
|
// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
#include "ARMInstrInfo.h"
|
||||||
|
#include "ARM.h"
|
||||||
|
#include "ARMGenInstrInfo.inc"
|
||||||
|
#include "ARMMachineFunctionInfo.h"
|
||||||
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||||
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||||
|
#include "llvm/ADT/SmallVector.h"
|
||||||
|
#include "Thumb1InstrInfo.h"
|
||||||
|
|
||||||
|
using namespace llvm;
|
||||||
|
|
||||||
|
Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
|
||||||
|
: ARMBaseInstrInfo(STI), RI(*this, STI) {
|
||||||
|
}
|
||||||
|
|
||||||
|
bool Thumb1InstrInfo::isMoveInstr(const MachineInstr &MI,
|
||||||
|
unsigned &SrcReg, unsigned &DstReg,
|
||||||
|
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
|
||||||
|
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
|
||||||
|
|
||||||
|
unsigned oc = MI.getOpcode();
|
||||||
|
switch (oc) {
|
||||||
|
default:
|
||||||
|
return false;
|
||||||
|
case ARM::tMOVr:
|
||||||
|
case ARM::tMOVhir2lor:
|
||||||
|
case ARM::tMOVlor2hir:
|
||||||
|
case ARM::tMOVhir2hir:
|
||||||
|
assert(MI.getDesc().getNumOperands() >= 2 &&
|
||||||
|
MI.getOperand(0).isReg() &&
|
||||||
|
MI.getOperand(1).isReg() &&
|
||||||
|
"Invalid Thumb MOV instruction");
|
||||||
|
SrcReg = MI.getOperand(1).getReg();
|
||||||
|
DstReg = MI.getOperand(0).getReg();
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
||||||
|
int &FrameIndex) const {
|
||||||
|
switch (MI->getOpcode()) {
|
||||||
|
default: break;
|
||||||
|
case ARM::tRestore:
|
||||||
|
if (MI->getOperand(1).isFI() &&
|
||||||
|
MI->getOperand(2).isImm() &&
|
||||||
|
MI->getOperand(2).getImm() == 0) {
|
||||||
|
FrameIndex = MI->getOperand(1).getIndex();
|
||||||
|
return MI->getOperand(0).getReg();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned Thumb1InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
|
||||||
|
int &FrameIndex) const {
|
||||||
|
switch (MI->getOpcode()) {
|
||||||
|
default: break;
|
||||||
|
case ARM::tSpill:
|
||||||
|
if (MI->getOperand(1).isFI() &&
|
||||||
|
MI->getOperand(2).isImm() &&
|
||||||
|
MI->getOperand(2).getImm() == 0) {
|
||||||
|
FrameIndex = MI->getOperand(1).getIndex();
|
||||||
|
return MI->getOperand(0).getReg();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator I,
|
||||||
|
unsigned DestReg, unsigned SrcReg,
|
||||||
|
const TargetRegisterClass *DestRC,
|
||||||
|
const TargetRegisterClass *SrcRC) const {
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||||
|
|
||||||
|
if (DestRC == ARM::GPRRegisterClass) {
|
||||||
|
if (SrcRC == ARM::GPRRegisterClass) {
|
||||||
|
BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
|
||||||
|
return true;
|
||||||
|
} else if (SrcRC == ARM::tGPRRegisterClass) {
|
||||||
|
BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
} else if (DestRC == ARM::tGPRRegisterClass) {
|
||||||
|
if (SrcRC == ARM::GPRRegisterClass) {
|
||||||
|
BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
|
||||||
|
return true;
|
||||||
|
} else if (SrcRC == ARM::tGPRRegisterClass) {
|
||||||
|
BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool Thumb1InstrInfo::
|
||||||
|
canFoldMemoryOperand(const MachineInstr *MI,
|
||||||
|
const SmallVectorImpl<unsigned> &Ops) const {
|
||||||
|
if (Ops.size() != 1) return false;
|
||||||
|
|
||||||
|
unsigned OpNum = Ops[0];
|
||||||
|
unsigned Opc = MI->getOpcode();
|
||||||
|
switch (Opc) {
|
||||||
|
default: break;
|
||||||
|
case ARM::tMOVr:
|
||||||
|
case ARM::tMOVlor2hir:
|
||||||
|
case ARM::tMOVhir2lor:
|
||||||
|
case ARM::tMOVhir2hir: {
|
||||||
|
if (OpNum == 0) { // move -> store
|
||||||
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
||||||
|
if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
|
||||||
|
// tSpill cannot take a high register operand.
|
||||||
|
return false;
|
||||||
|
} else { // move -> load
|
||||||
|
unsigned DstReg = MI->getOperand(0).getReg();
|
||||||
|
if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
|
||||||
|
// tRestore cannot target a high register operand.
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
void Thumb1InstrInfo::
|
||||||
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned SrcReg, bool isKill, int FI,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||||
|
|
||||||
|
assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
|
||||||
|
|
||||||
|
if (RC == ARM::tGPRRegisterClass) {
|
||||||
|
BuildMI(MBB, I, DL, get(ARM::tSpill))
|
||||||
|
.addReg(SrcReg, getKillRegState(isKill))
|
||||||
|
.addFrameIndex(FI).addImm(0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void Thumb1InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
unsigned Opc = 0;
|
||||||
|
|
||||||
|
assert(RC == ARM::GPRRegisterClass && "Unknown regclass!");
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstrBuilder MIB =
|
||||||
|
BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB.addOperand(Addr[i]);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
void Thumb1InstrInfo::
|
||||||
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned DestReg, int FI,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||||
|
|
||||||
|
assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
|
||||||
|
|
||||||
|
if (RC == ARM::tGPRRegisterClass) {
|
||||||
|
BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
|
||||||
|
.addFrameIndex(FI).addImm(0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void Thumb1InstrInfo::
|
||||||
|
loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
unsigned Opc = 0;
|
||||||
|
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB.addOperand(Addr[i]);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool Thumb1InstrInfo::
|
||||||
|
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
const std::vector<CalleeSavedInfo> &CSI) const {
|
||||||
|
if (CSI.empty())
|
||||||
|
return false;
|
||||||
|
|
||||||
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
|
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||||
|
|
||||||
|
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
|
||||||
|
for (unsigned i = CSI.size(); i != 0; --i) {
|
||||||
|
unsigned Reg = CSI[i-1].getReg();
|
||||||
|
// Add the callee-saved register as live-in. It's killed at the spill.
|
||||||
|
MBB.addLiveIn(Reg);
|
||||||
|
MIB.addReg(Reg, RegState::Kill);
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool Thumb1InstrInfo::
|
||||||
|
restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
const std::vector<CalleeSavedInfo> &CSI) const {
|
||||||
|
MachineFunction &MF = *MBB.getParent();
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
if (CSI.empty())
|
||||||
|
return false;
|
||||||
|
|
||||||
|
bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
|
||||||
|
MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
|
||||||
|
for (unsigned i = CSI.size(); i != 0; --i) {
|
||||||
|
unsigned Reg = CSI[i-1].getReg();
|
||||||
|
if (Reg == ARM::LR) {
|
||||||
|
// Special epilogue for vararg functions. See emitEpilogue
|
||||||
|
if (isVarArg)
|
||||||
|
continue;
|
||||||
|
Reg = ARM::PC;
|
||||||
|
PopMI->setDesc(get(ARM::tPOP_RET));
|
||||||
|
MI = MBB.erase(MI);
|
||||||
|
}
|
||||||
|
PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
|
||||||
|
}
|
||||||
|
|
||||||
|
// It's illegal to emit pop instruction without operands.
|
||||||
|
if (PopMI->getNumOperands() > 0)
|
||||||
|
MBB.insert(MI, PopMI);
|
||||||
|
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstr *Thumb1InstrInfo::
|
||||||
|
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
|
||||||
|
const SmallVectorImpl<unsigned> &Ops, int FI) const {
|
||||||
|
if (Ops.size() != 1) return NULL;
|
||||||
|
|
||||||
|
unsigned OpNum = Ops[0];
|
||||||
|
unsigned Opc = MI->getOpcode();
|
||||||
|
MachineInstr *NewMI = NULL;
|
||||||
|
switch (Opc) {
|
||||||
|
default: break;
|
||||||
|
case ARM::tMOVr:
|
||||||
|
case ARM::tMOVlor2hir:
|
||||||
|
case ARM::tMOVhir2lor:
|
||||||
|
case ARM::tMOVhir2hir: {
|
||||||
|
if (OpNum == 0) { // move -> store
|
||||||
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
||||||
|
bool isKill = MI->getOperand(1).isKill();
|
||||||
|
if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
|
||||||
|
// tSpill cannot take a high register operand.
|
||||||
|
break;
|
||||||
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
|
||||||
|
.addReg(SrcReg, getKillRegState(isKill))
|
||||||
|
.addFrameIndex(FI).addImm(0);
|
||||||
|
} else { // move -> load
|
||||||
|
unsigned DstReg = MI->getOperand(0).getReg();
|
||||||
|
if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
|
||||||
|
// tRestore cannot target a high register operand.
|
||||||
|
break;
|
||||||
|
bool isDead = MI->getOperand(0).isDead();
|
||||||
|
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
|
||||||
|
.addReg(DstReg, RegState::Define | getDeadRegState(isDead))
|
||||||
|
.addFrameIndex(FI).addImm(0);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return NewMI;
|
||||||
|
}
|
93
lib/Target/ARM/Thumb1InstrInfo.h
Normal file
93
lib/Target/ARM/Thumb1InstrInfo.h
Normal file
@ -0,0 +1,93 @@
|
|||||||
|
//===- Thumb1InstrInfo.h - Thumb-1 Instruction Information ----------*- C++ -*-===//
|
||||||
|
//
|
||||||
|
// The LLVM Compiler Infrastructure
|
||||||
|
//
|
||||||
|
// This file is distributed under the University of Illinois Open Source
|
||||||
|
// License. See LICENSE.TXT for details.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
//
|
||||||
|
// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
#ifndef THUMB1INSTRUCTIONINFO_H
|
||||||
|
#define THUMB1INSTRUCTIONINFO_H
|
||||||
|
|
||||||
|
#include "llvm/Target/TargetInstrInfo.h"
|
||||||
|
#include "ARM.h"
|
||||||
|
#include "ARMInstrInfo.h"
|
||||||
|
#include "Thumb1RegisterInfo.h"
|
||||||
|
|
||||||
|
namespace llvm {
|
||||||
|
class ARMSubtarget;
|
||||||
|
|
||||||
|
class Thumb1InstrInfo : public ARMBaseInstrInfo {
|
||||||
|
Thumb1RegisterInfo RI;
|
||||||
|
public:
|
||||||
|
explicit Thumb1InstrInfo(const ARMSubtarget &STI);
|
||||||
|
|
||||||
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
||||||
|
/// such, whenever a client has an instance of instruction info, it should
|
||||||
|
/// always be able to get register info as well (through this method).
|
||||||
|
///
|
||||||
|
const Thumb1RegisterInfo &getRegisterInfo() const { return RI; }
|
||||||
|
|
||||||
|
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
||||||
|
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
||||||
|
|
||||||
|
bool isMoveInstr(const MachineInstr &MI,
|
||||||
|
unsigned &SrcReg, unsigned &DstReg,
|
||||||
|
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
|
||||||
|
unsigned isLoadFromStackSlot(const MachineInstr *MI,
|
||||||
|
int &FrameIndex) const;
|
||||||
|
unsigned isStoreToStackSlot(const MachineInstr *MI,
|
||||||
|
int &FrameIndex) const;
|
||||||
|
|
||||||
|
bool copyRegToReg(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator I,
|
||||||
|
unsigned DestReg, unsigned SrcReg,
|
||||||
|
const TargetRegisterClass *DestRC,
|
||||||
|
const TargetRegisterClass *SrcRC) const;
|
||||||
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned DestReg, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
bool canFoldMemoryOperand(const MachineInstr *MI,
|
||||||
|
const SmallVectorImpl<unsigned> &Ops) const;
|
||||||
|
|
||||||
|
MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
||||||
|
MachineInstr* MI,
|
||||||
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
|
int FrameIndex) const;
|
||||||
|
|
||||||
|
MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
||||||
|
MachineInstr* MI,
|
||||||
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
|
MachineInstr* LoadMI) const {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // THUMB1INSTRUCTIONINFO_H
|
@ -1,4 +1,4 @@
|
|||||||
//===- ThumbRegisterInfo.cpp - Thumb Register Information -------*- C++ -*-===//
|
//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
|
||||||
//
|
//
|
||||||
// The LLVM Compiler Infrastructure
|
// The LLVM Compiler Infrastructure
|
||||||
//
|
//
|
||||||
@ -7,7 +7,7 @@
|
|||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
//
|
//
|
||||||
// This file contains the ARM implementation of the TargetRegisterInfo class.
|
// This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
|
||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
@ -15,8 +15,8 @@
|
|||||||
#include "ARMAddressingModes.h"
|
#include "ARMAddressingModes.h"
|
||||||
#include "ARMMachineFunctionInfo.h"
|
#include "ARMMachineFunctionInfo.h"
|
||||||
#include "ARMSubtarget.h"
|
#include "ARMSubtarget.h"
|
||||||
#include "ThumbInstrInfo.h"
|
#include "Thumb1InstrInfo.h"
|
||||||
#include "ThumbRegisterInfo.h"
|
#include "Thumb1RegisterInfo.h"
|
||||||
#include "llvm/Constants.h"
|
#include "llvm/Constants.h"
|
||||||
#include "llvm/DerivedTypes.h"
|
#include "llvm/DerivedTypes.h"
|
||||||
#include "llvm/CodeGen/MachineConstantPool.h"
|
#include "llvm/CodeGen/MachineConstantPool.h"
|
||||||
@ -37,18 +37,18 @@ ThumbRegScavenging("enable-thumb-reg-scavenging",
|
|||||||
cl::Hidden,
|
cl::Hidden,
|
||||||
cl::desc("Enable register scavenging on Thumb"));
|
cl::desc("Enable register scavenging on Thumb"));
|
||||||
|
|
||||||
ThumbRegisterInfo::ThumbRegisterInfo(const TargetInstrInfo &tii,
|
Thumb1RegisterInfo::Thumb1RegisterInfo(const TargetInstrInfo &tii,
|
||||||
const ARMSubtarget &sti)
|
const ARMSubtarget &sti)
|
||||||
: ARMBaseRegisterInfo(tii, sti) {
|
: ARMBaseRegisterInfo(tii, sti) {
|
||||||
}
|
}
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||||
/// specified immediate.
|
/// specified immediate.
|
||||||
void ThumbRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
unsigned DestReg, int Val,
|
unsigned DestReg, int Val,
|
||||||
const TargetInstrInfo *TII,
|
const TargetInstrInfo *TII,
|
||||||
DebugLoc dl) const {
|
DebugLoc dl) const {
|
||||||
MachineFunction &MF = *MBB.getParent();
|
MachineFunction &MF = *MBB.getParent();
|
||||||
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
||||||
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
|
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
|
||||||
@ -59,7 +59,7 @@ void ThumbRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
|||||||
}
|
}
|
||||||
|
|
||||||
const TargetRegisterClass*
|
const TargetRegisterClass*
|
||||||
ThumbRegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
|
Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
|
||||||
if (isARMLowRegister(Reg))
|
if (isARMLowRegister(Reg))
|
||||||
return ARM::tGPRRegisterClass;
|
return ARM::tGPRRegisterClass;
|
||||||
switch (Reg) {
|
switch (Reg) {
|
||||||
@ -74,11 +74,11 @@ ThumbRegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
|
|||||||
}
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
ThumbRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
|
Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
|
||||||
return ThumbRegScavenging;
|
return ThumbRegScavenging;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool ThumbRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
|
bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
|
||||||
const MachineFrameInfo *FFI = MF.getFrameInfo();
|
const MachineFrameInfo *FFI = MF.getFrameInfo();
|
||||||
unsigned CFSize = FFI->getMaxCallFrameSize();
|
unsigned CFSize = FFI->getMaxCallFrameSize();
|
||||||
// It's not always a good idea to include the call frame as part of the
|
// It's not always a good idea to include the call frame as part of the
|
||||||
@ -101,7 +101,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
|
|||||||
unsigned DestReg, unsigned BaseReg,
|
unsigned DestReg, unsigned BaseReg,
|
||||||
int NumBytes, bool CanChangeCC,
|
int NumBytes, bool CanChangeCC,
|
||||||
const TargetInstrInfo &TII,
|
const TargetInstrInfo &TII,
|
||||||
const ThumbRegisterInfo& MRI,
|
const Thumb1RegisterInfo& MRI,
|
||||||
DebugLoc dl) {
|
DebugLoc dl) {
|
||||||
bool isHigh = !isARMLowRegister(DestReg) ||
|
bool isHigh = !isARMLowRegister(DestReg) ||
|
||||||
(BaseReg != 0 && !isARMLowRegister(BaseReg));
|
(BaseReg != 0 && !isARMLowRegister(BaseReg));
|
||||||
@ -175,7 +175,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
|
|||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
unsigned DestReg, unsigned BaseReg,
|
unsigned DestReg, unsigned BaseReg,
|
||||||
int NumBytes, const TargetInstrInfo &TII,
|
int NumBytes, const TargetInstrInfo &TII,
|
||||||
const ThumbRegisterInfo& MRI,
|
const Thumb1RegisterInfo& MRI,
|
||||||
DebugLoc dl) {
|
DebugLoc dl) {
|
||||||
bool isSub = NumBytes < 0;
|
bool isSub = NumBytes < 0;
|
||||||
unsigned Bytes = (unsigned)NumBytes;
|
unsigned Bytes = (unsigned)NumBytes;
|
||||||
@ -279,13 +279,13 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
|
|||||||
static void emitSPUpdate(MachineBasicBlock &MBB,
|
static void emitSPUpdate(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
const TargetInstrInfo &TII, DebugLoc dl,
|
const TargetInstrInfo &TII, DebugLoc dl,
|
||||||
const ThumbRegisterInfo &MRI,
|
const Thumb1RegisterInfo &MRI,
|
||||||
int NumBytes) {
|
int NumBytes) {
|
||||||
emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
|
emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
|
||||||
MRI, dl);
|
MRI, dl);
|
||||||
}
|
}
|
||||||
|
|
||||||
void ThumbRegisterInfo::
|
void Thumb1RegisterInfo::
|
||||||
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I) const {
|
MachineBasicBlock::iterator I) const {
|
||||||
if (!hasReservedCallFrame(MF)) {
|
if (!hasReservedCallFrame(MF)) {
|
||||||
@ -321,7 +321,7 @@ static void emitThumbConstant(MachineBasicBlock &MBB,
|
|||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
unsigned DestReg, int Imm,
|
unsigned DestReg, int Imm,
|
||||||
const TargetInstrInfo &TII,
|
const TargetInstrInfo &TII,
|
||||||
const ThumbRegisterInfo& MRI,
|
const Thumb1RegisterInfo& MRI,
|
||||||
DebugLoc dl) {
|
DebugLoc dl) {
|
||||||
bool isSub = Imm < 0;
|
bool isSub = Imm < 0;
|
||||||
if (isSub) Imm = -Imm;
|
if (isSub) Imm = -Imm;
|
||||||
@ -337,8 +337,8 @@ static void emitThumbConstant(MachineBasicBlock &MBB,
|
|||||||
.addReg(DestReg, RegState::Kill);
|
.addReg(DestReg, RegState::Kill);
|
||||||
}
|
}
|
||||||
|
|
||||||
void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||||
int SPAdj, RegScavenger *RS) const{
|
int SPAdj, RegScavenger *RS) const{
|
||||||
unsigned i = 0;
|
unsigned i = 0;
|
||||||
MachineInstr &MI = *II;
|
MachineInstr &MI = *II;
|
||||||
MachineBasicBlock &MBB = *MI.getParent();
|
MachineBasicBlock &MBB = *MI.getParent();
|
||||||
@ -566,7 +566,7 @@ void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||||||
assert(false && "Unexpected opcode!");
|
assert(false && "Unexpected opcode!");
|
||||||
}
|
}
|
||||||
|
|
||||||
void ThumbRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||||
MachineBasicBlock &MBB = MF.front();
|
MachineBasicBlock &MBB = MF.front();
|
||||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||||
@ -690,8 +690,8 @@ static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
|
|||||||
isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
|
isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
|
||||||
}
|
}
|
||||||
|
|
||||||
void ThumbRegisterInfo::emitEpilogue(MachineFunction &MF,
|
void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
|
||||||
MachineBasicBlock &MBB) const {
|
MachineBasicBlock &MBB) const {
|
||||||
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
||||||
assert((MBBI->getOpcode() == ARM::tBX_RET ||
|
assert((MBBI->getOpcode() == ARM::tBX_RET ||
|
||||||
MBBI->getOpcode() == ARM::tPOP_RET) &&
|
MBBI->getOpcode() == ARM::tPOP_RET) &&
|
@ -1,4 +1,4 @@
|
|||||||
//===- ThumbRegisterInfo.h - Thumb Register Information Impl ----*- C++ -*-===//
|
//===- Thumb1RegisterInfo.h - Thumb-1 Register Information Impl ----*- C++ -*-===//
|
||||||
//
|
//
|
||||||
// The LLVM Compiler Infrastructure
|
// The LLVM Compiler Infrastructure
|
||||||
//
|
//
|
||||||
@ -7,12 +7,12 @@
|
|||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
//
|
//
|
||||||
// This file contains the ARM implementation of the TargetRegisterInfo class.
|
// This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
|
||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
#ifndef THUMBREGISTERINFO_H
|
#ifndef THUMB1REGISTERINFO_H
|
||||||
#define THUMBREGISTERINFO_H
|
#define THUMB1REGISTERINFO_H
|
||||||
|
|
||||||
#include "ARM.h"
|
#include "ARM.h"
|
||||||
#include "ARMRegisterInfo.h"
|
#include "ARMRegisterInfo.h"
|
||||||
@ -23,9 +23,9 @@ namespace llvm {
|
|||||||
class TargetInstrInfo;
|
class TargetInstrInfo;
|
||||||
class Type;
|
class Type;
|
||||||
|
|
||||||
struct ThumbRegisterInfo : public ARMBaseRegisterInfo {
|
struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
|
||||||
public:
|
public:
|
||||||
ThumbRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
|
Thumb1RegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||||
/// specified immediate.
|
/// specified immediate.
|
||||||
@ -57,4 +57,4 @@ public:
|
|||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // THUMBREGISTERINFO_H
|
#endif // THUMB1REGISTERINFO_H
|
@ -1,4 +1,4 @@
|
|||||||
//===- ThumbInstrInfo.cpp - Thumb Instruction Information --------*- C++ -*-===//
|
//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------*- C++ -*-===//
|
||||||
//
|
//
|
||||||
// The LLVM Compiler Infrastructure
|
// The LLVM Compiler Infrastructure
|
||||||
//
|
//
|
||||||
@ -7,7 +7,7 @@
|
|||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
//
|
//
|
||||||
// This file contains the Thumb implementation of the TargetInstrInfo class.
|
// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
|
||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
@ -18,17 +18,17 @@
|
|||||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||||
#include "llvm/ADT/SmallVector.h"
|
#include "llvm/ADT/SmallVector.h"
|
||||||
#include "ThumbInstrInfo.h"
|
#include "Thumb2InstrInfo.h"
|
||||||
|
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
ThumbInstrInfo::ThumbInstrInfo(const ARMSubtarget &STI)
|
Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
|
||||||
: ARMBaseInstrInfo(STI), RI(*this, STI) {
|
: ARMBaseInstrInfo(STI), RI(*this, STI) {
|
||||||
}
|
}
|
||||||
|
|
||||||
bool ThumbInstrInfo::isMoveInstr(const MachineInstr &MI,
|
bool Thumb2InstrInfo::isMoveInstr(const MachineInstr &MI,
|
||||||
unsigned &SrcReg, unsigned &DstReg,
|
unsigned &SrcReg, unsigned &DstReg,
|
||||||
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
|
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
|
||||||
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
|
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
|
||||||
|
|
||||||
unsigned oc = MI.getOpcode();
|
unsigned oc = MI.getOpcode();
|
||||||
@ -50,8 +50,8 @@ bool ThumbInstrInfo::isMoveInstr(const MachineInstr &MI,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned ThumbInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
unsigned Thumb2InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
||||||
int &FrameIndex) const {
|
int &FrameIndex) const {
|
||||||
switch (MI->getOpcode()) {
|
switch (MI->getOpcode()) {
|
||||||
default: break;
|
default: break;
|
||||||
// FIXME: Thumb2
|
// FIXME: Thumb2
|
||||||
@ -67,8 +67,8 @@ unsigned ThumbInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned ThumbInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
|
unsigned Thumb2InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
|
||||||
int &FrameIndex) const {
|
int &FrameIndex) const {
|
||||||
switch (MI->getOpcode()) {
|
switch (MI->getOpcode()) {
|
||||||
default: break;
|
default: break;
|
||||||
// FIXME: Thumb2
|
// FIXME: Thumb2
|
||||||
@ -84,11 +84,11 @@ unsigned ThumbInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool ThumbInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
bool Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const {
|
const TargetRegisterClass *SrcRC) const {
|
||||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
if (I != MBB.end()) DL = I->getDebugLoc();
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||||
|
|
||||||
@ -114,7 +114,7 @@ bool ThumbInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool ThumbInstrInfo::
|
bool Thumb2InstrInfo::
|
||||||
canFoldMemoryOperand(const MachineInstr *MI,
|
canFoldMemoryOperand(const MachineInstr *MI,
|
||||||
const SmallVectorImpl<unsigned> &Ops) const {
|
const SmallVectorImpl<unsigned> &Ops) const {
|
||||||
if (Ops.size() != 1) return false;
|
if (Ops.size() != 1) return false;
|
||||||
@ -145,7 +145,7 @@ canFoldMemoryOperand(const MachineInstr *MI,
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
void ThumbInstrInfo::
|
void Thumb2InstrInfo::
|
||||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
unsigned SrcReg, bool isKill, int FI,
|
unsigned SrcReg, bool isKill, int FI,
|
||||||
const TargetRegisterClass *RC) const {
|
const TargetRegisterClass *RC) const {
|
||||||
@ -162,11 +162,11 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void ThumbInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
void Thumb2InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
bool isKill,
|
bool isKill,
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
const TargetRegisterClass *RC,
|
const TargetRegisterClass *RC,
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
||||||
DebugLoc DL = DebugLoc::getUnknownLoc();
|
DebugLoc DL = DebugLoc::getUnknownLoc();
|
||||||
unsigned Opc = 0;
|
unsigned Opc = 0;
|
||||||
|
|
||||||
@ -184,7 +184,7 @@ void ThumbInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
void ThumbInstrInfo::
|
void Thumb2InstrInfo::
|
||||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg, int FI,
|
unsigned DestReg, int FI,
|
||||||
const TargetRegisterClass *RC) const {
|
const TargetRegisterClass *RC) const {
|
||||||
@ -200,7 +200,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void ThumbInstrInfo::
|
void Thumb2InstrInfo::
|
||||||
loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
const TargetRegisterClass *RC,
|
const TargetRegisterClass *RC,
|
||||||
@ -220,7 +220,7 @@ loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool ThumbInstrInfo::
|
bool Thumb2InstrInfo::
|
||||||
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
const std::vector<CalleeSavedInfo> &CSI) const {
|
const std::vector<CalleeSavedInfo> &CSI) const {
|
||||||
@ -240,7 +240,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool ThumbInstrInfo::
|
bool Thumb2InstrInfo::
|
||||||
restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
const std::vector<CalleeSavedInfo> &CSI) const {
|
const std::vector<CalleeSavedInfo> &CSI) const {
|
||||||
@ -271,7 +271,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
MachineInstr *ThumbInstrInfo::
|
MachineInstr *Thumb2InstrInfo::
|
||||||
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
|
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
|
||||||
const SmallVectorImpl<unsigned> &Ops, int FI) const {
|
const SmallVectorImpl<unsigned> &Ops, int FI) const {
|
||||||
if (Ops.size() != 1) return NULL;
|
if (Ops.size() != 1) return NULL;
|
@ -1,4 +1,4 @@
|
|||||||
//===- ThumbInstrInfo.h - Thumb Instruction Information ----------*- C++ -*-===//
|
//===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ----------*- C++ -*-===//
|
||||||
//
|
//
|
||||||
// The LLVM Compiler Infrastructure
|
// The LLVM Compiler Infrastructure
|
||||||
//
|
//
|
||||||
@ -7,89 +7,87 @@
|
|||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
//
|
//
|
||||||
// This file contains the ARM implementation of the TargetInstrInfo class.
|
// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
|
||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
#ifndef THUMBINSTRUCTIONINFO_H
|
#ifndef THUMB2INSTRUCTIONINFO_H
|
||||||
#define THUMBINSTRUCTIONINFO_H
|
#define THUMB2INSTRUCTIONINFO_H
|
||||||
|
|
||||||
#include "llvm/Target/TargetInstrInfo.h"
|
#include "llvm/Target/TargetInstrInfo.h"
|
||||||
#include "ARM.h"
|
#include "ARM.h"
|
||||||
#include "ARMInstrInfo.h"
|
#include "ARMInstrInfo.h"
|
||||||
#include "ThumbRegisterInfo.h"
|
#include "Thumb2RegisterInfo.h"
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
class ARMSubtarget;
|
class ARMSubtarget;
|
||||||
|
|
||||||
class ThumbInstrInfo : public ARMBaseInstrInfo {
|
class Thumb2InstrInfo : public ARMBaseInstrInfo {
|
||||||
ThumbRegisterInfo RI;
|
Thumb2RegisterInfo RI;
|
||||||
public:
|
public:
|
||||||
explicit ThumbInstrInfo(const ARMSubtarget &STI);
|
explicit Thumb2InstrInfo(const ARMSubtarget &STI);
|
||||||
|
|
||||||
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
||||||
/// such, whenever a client has an instance of instruction info, it should
|
/// such, whenever a client has an instance of instruction info, it should
|
||||||
/// always be able to get register info as well (through this method).
|
/// always be able to get register info as well (through this method).
|
||||||
///
|
///
|
||||||
virtual const ThumbRegisterInfo &getRegisterInfo() const { return RI; }
|
const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
|
||||||
|
|
||||||
/// Return true if the instruction is a register to register move and return
|
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||||
/// the source and dest operands and their sub-register indices by reference.
|
MachineBasicBlock::iterator MI,
|
||||||
virtual bool isMoveInstr(const MachineInstr &MI,
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
||||||
|
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
||||||
|
|
||||||
|
bool isMoveInstr(const MachineInstr &MI,
|
||||||
unsigned &SrcReg, unsigned &DstReg,
|
unsigned &SrcReg, unsigned &DstReg,
|
||||||
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
|
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
|
||||||
|
unsigned isLoadFromStackSlot(const MachineInstr *MI,
|
||||||
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
|
|
||||||
int &FrameIndex) const;
|
int &FrameIndex) const;
|
||||||
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
|
unsigned isStoreToStackSlot(const MachineInstr *MI,
|
||||||
int &FrameIndex) const;
|
int &FrameIndex) const;
|
||||||
|
|
||||||
virtual bool copyRegToReg(MachineBasicBlock &MBB,
|
bool copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const;
|
const TargetRegisterClass *SrcRC) const;
|
||||||
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MBBI,
|
MachineBasicBlock::iterator MBBI,
|
||||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
const TargetRegisterClass *RC) const;
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
const TargetRegisterClass *RC,
|
const TargetRegisterClass *RC,
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MBBI,
|
MachineBasicBlock::iterator MBBI,
|
||||||
unsigned DestReg, int FrameIndex,
|
unsigned DestReg, int FrameIndex,
|
||||||
const TargetRegisterClass *RC) const;
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
const TargetRegisterClass *RC,
|
const TargetRegisterClass *RC,
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
||||||
virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
const std::vector<CalleeSavedInfo> &CSI) const;
|
|
||||||
|
|
||||||
virtual bool canFoldMemoryOperand(const MachineInstr *MI,
|
bool canFoldMemoryOperand(const MachineInstr *MI,
|
||||||
const SmallVectorImpl<unsigned> &Ops) const;
|
const SmallVectorImpl<unsigned> &Ops) const;
|
||||||
|
|
||||||
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
||||||
MachineInstr* MI,
|
MachineInstr* MI,
|
||||||
const SmallVectorImpl<unsigned> &Ops,
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
MachineInstr* LoadMI) const {
|
int FrameIndex) const;
|
||||||
|
|
||||||
|
MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
||||||
|
MachineInstr* MI,
|
||||||
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
|
MachineInstr* LoadMI) const {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
||||||
MachineInstr* MI,
|
|
||||||
const SmallVectorImpl<unsigned> &Ops,
|
|
||||||
int FrameIndex) const;
|
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // THUMBINSTRUCTIONINFO_H
|
#endif // THUMB2INSTRUCTIONINFO_H
|
755
lib/Target/ARM/Thumb2RegisterInfo.cpp
Normal file
755
lib/Target/ARM/Thumb2RegisterInfo.cpp
Normal file
@ -0,0 +1,755 @@
|
|||||||
|
//===- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------*- C++ -*-===//
|
||||||
|
//
|
||||||
|
// The LLVM Compiler Infrastructure
|
||||||
|
//
|
||||||
|
// This file is distributed under the University of Illinois Open Source
|
||||||
|
// License. See LICENSE.TXT for details.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
//
|
||||||
|
// This file contains the Thumb-2 implementation of the TargetRegisterInfo class.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
#include "ARM.h"
|
||||||
|
#include "ARMAddressingModes.h"
|
||||||
|
#include "ARMMachineFunctionInfo.h"
|
||||||
|
#include "ARMSubtarget.h"
|
||||||
|
#include "Thumb2InstrInfo.h"
|
||||||
|
#include "Thumb2RegisterInfo.h"
|
||||||
|
#include "llvm/Constants.h"
|
||||||
|
#include "llvm/DerivedTypes.h"
|
||||||
|
#include "llvm/CodeGen/MachineConstantPool.h"
|
||||||
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||||
|
#include "llvm/CodeGen/MachineFunction.h"
|
||||||
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||||
|
#include "llvm/CodeGen/MachineLocation.h"
|
||||||
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||||
|
#include "llvm/Target/TargetFrameInfo.h"
|
||||||
|
#include "llvm/Target/TargetMachine.h"
|
||||||
|
#include "llvm/ADT/BitVector.h"
|
||||||
|
#include "llvm/ADT/SmallVector.h"
|
||||||
|
#include "llvm/Support/CommandLine.h"
|
||||||
|
using namespace llvm;
|
||||||
|
|
||||||
|
static cl::opt<bool>
|
||||||
|
Thumb2RegScavenging("enable-thumb2-reg-scavenging",
|
||||||
|
cl::Hidden,
|
||||||
|
cl::desc("Enable register scavenging on Thumb-2"));
|
||||||
|
|
||||||
|
Thumb2RegisterInfo::Thumb2RegisterInfo(const TargetInstrInfo &tii,
|
||||||
|
const ARMSubtarget &sti)
|
||||||
|
: ARMBaseRegisterInfo(tii, sti) {
|
||||||
|
}
|
||||||
|
|
||||||
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||||
|
/// specified immediate.
|
||||||
|
void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
unsigned DestReg, int Val,
|
||||||
|
const TargetInstrInfo *TII,
|
||||||
|
DebugLoc dl) const {
|
||||||
|
MachineFunction &MF = *MBB.getParent();
|
||||||
|
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
||||||
|
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
|
||||||
|
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
|
||||||
|
|
||||||
|
BuildMI(MBB, MBBI, dl, TII->get(ARM::tLDRcp), DestReg)
|
||||||
|
.addConstantPoolIndex(Idx);
|
||||||
|
}
|
||||||
|
|
||||||
|
const TargetRegisterClass*
|
||||||
|
Thumb2RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
|
||||||
|
if (isARMLowRegister(Reg))
|
||||||
|
return ARM::tGPRRegisterClass;
|
||||||
|
switch (Reg) {
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
|
||||||
|
case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
|
||||||
|
return ARM::GPRRegisterClass;
|
||||||
|
}
|
||||||
|
|
||||||
|
return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
|
||||||
|
}
|
||||||
|
|
||||||
|
bool
|
||||||
|
Thumb2RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
|
||||||
|
return Thumb2RegScavenging;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool Thumb2RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
|
||||||
|
const MachineFrameInfo *FFI = MF.getFrameInfo();
|
||||||
|
unsigned CFSize = FFI->getMaxCallFrameSize();
|
||||||
|
// It's not always a good idea to include the call frame as part of the
|
||||||
|
// stack frame. ARM (especially Thumb) has small immediate offset to
|
||||||
|
// address the stack frame. So a large call frame can cause poor codegen
|
||||||
|
// and may even makes it impossible to scavenge a register.
|
||||||
|
if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
|
||||||
|
return false;
|
||||||
|
|
||||||
|
return !MF.getFrameInfo()->hasVarSizedObjects();
|
||||||
|
}
|
||||||
|
|
||||||
|
/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
|
||||||
|
/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
|
||||||
|
/// in a register using mov / mvn sequences or load the immediate from a
|
||||||
|
/// constpool entry.
|
||||||
|
static
|
||||||
|
void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
unsigned DestReg, unsigned BaseReg,
|
||||||
|
int NumBytes, bool CanChangeCC,
|
||||||
|
const TargetInstrInfo &TII,
|
||||||
|
const Thumb2RegisterInfo& MRI,
|
||||||
|
DebugLoc dl) {
|
||||||
|
bool isHigh = !isARMLowRegister(DestReg) ||
|
||||||
|
(BaseReg != 0 && !isARMLowRegister(BaseReg));
|
||||||
|
bool isSub = false;
|
||||||
|
// Subtract doesn't have high register version. Load the negative value
|
||||||
|
// if either base or dest register is a high register. Also, if do not
|
||||||
|
// issue sub as part of the sequence if condition register is to be
|
||||||
|
// preserved.
|
||||||
|
if (NumBytes < 0 && !isHigh && CanChangeCC) {
|
||||||
|
isSub = true;
|
||||||
|
NumBytes = -NumBytes;
|
||||||
|
}
|
||||||
|
unsigned LdReg = DestReg;
|
||||||
|
if (DestReg == ARM::SP) {
|
||||||
|
assert(BaseReg == ARM::SP && "Unexpected!");
|
||||||
|
LdReg = ARM::R3;
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
|
||||||
|
.addReg(ARM::R3, RegState::Kill);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (NumBytes <= 255 && NumBytes >= 0)
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
|
||||||
|
else if (NumBytes < 0 && NumBytes >= -255) {
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
|
||||||
|
.addReg(LdReg, RegState::Kill);
|
||||||
|
} else
|
||||||
|
MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, &TII, dl);
|
||||||
|
|
||||||
|
// Emit add / sub.
|
||||||
|
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
|
||||||
|
const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl,
|
||||||
|
TII.get(Opc), DestReg);
|
||||||
|
if (DestReg == ARM::SP || isSub)
|
||||||
|
MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
|
||||||
|
else
|
||||||
|
MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
|
||||||
|
if (DestReg == ARM::SP)
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
|
||||||
|
.addReg(ARM::R12, RegState::Kill);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// calcNumMI - Returns the number of instructions required to materialize
|
||||||
|
/// the specific add / sub r, c instruction.
|
||||||
|
static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
|
||||||
|
unsigned NumBits, unsigned Scale) {
|
||||||
|
unsigned NumMIs = 0;
|
||||||
|
unsigned Chunk = ((1 << NumBits) - 1) * Scale;
|
||||||
|
|
||||||
|
if (Opc == ARM::tADDrSPi) {
|
||||||
|
unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
|
||||||
|
Bytes -= ThisVal;
|
||||||
|
NumMIs++;
|
||||||
|
NumBits = 8;
|
||||||
|
Scale = 1; // Followed by a number of tADDi8.
|
||||||
|
Chunk = ((1 << NumBits) - 1) * Scale;
|
||||||
|
}
|
||||||
|
|
||||||
|
NumMIs += Bytes / Chunk;
|
||||||
|
if ((Bytes % Chunk) != 0)
|
||||||
|
NumMIs++;
|
||||||
|
if (ExtraOpc)
|
||||||
|
NumMIs++;
|
||||||
|
return NumMIs;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
|
||||||
|
/// a destreg = basereg + immediate in Thumb code.
|
||||||
|
static
|
||||||
|
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
unsigned DestReg, unsigned BaseReg,
|
||||||
|
int NumBytes, const TargetInstrInfo &TII,
|
||||||
|
const Thumb2RegisterInfo& MRI,
|
||||||
|
DebugLoc dl) {
|
||||||
|
bool isSub = NumBytes < 0;
|
||||||
|
unsigned Bytes = (unsigned)NumBytes;
|
||||||
|
if (isSub) Bytes = -NumBytes;
|
||||||
|
bool isMul4 = (Bytes & 3) == 0;
|
||||||
|
bool isTwoAddr = false;
|
||||||
|
bool DstNotEqBase = false;
|
||||||
|
unsigned NumBits = 1;
|
||||||
|
unsigned Scale = 1;
|
||||||
|
int Opc = 0;
|
||||||
|
int ExtraOpc = 0;
|
||||||
|
|
||||||
|
if (DestReg == BaseReg && BaseReg == ARM::SP) {
|
||||||
|
assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
|
||||||
|
NumBits = 7;
|
||||||
|
Scale = 4;
|
||||||
|
Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
|
||||||
|
isTwoAddr = true;
|
||||||
|
} else if (!isSub && BaseReg == ARM::SP) {
|
||||||
|
// r1 = add sp, 403
|
||||||
|
// =>
|
||||||
|
// r1 = add sp, 100 * 4
|
||||||
|
// r1 = add r1, 3
|
||||||
|
if (!isMul4) {
|
||||||
|
Bytes &= ~3;
|
||||||
|
ExtraOpc = ARM::tADDi3;
|
||||||
|
}
|
||||||
|
NumBits = 8;
|
||||||
|
Scale = 4;
|
||||||
|
Opc = ARM::tADDrSPi;
|
||||||
|
} else {
|
||||||
|
// sp = sub sp, c
|
||||||
|
// r1 = sub sp, c
|
||||||
|
// r8 = sub sp, c
|
||||||
|
if (DestReg != BaseReg)
|
||||||
|
DstNotEqBase = true;
|
||||||
|
NumBits = 8;
|
||||||
|
Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
|
||||||
|
isTwoAddr = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
|
||||||
|
unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
|
||||||
|
if (NumMIs > Threshold) {
|
||||||
|
// This will expand into too many instructions. Load the immediate from a
|
||||||
|
// constpool entry.
|
||||||
|
emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
|
||||||
|
MRI, dl);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (DstNotEqBase) {
|
||||||
|
if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
|
||||||
|
// If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
|
||||||
|
unsigned Chunk = (1 << 3) - 1;
|
||||||
|
unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
|
||||||
|
Bytes -= ThisVal;
|
||||||
|
BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
|
||||||
|
.addReg(BaseReg, RegState::Kill).addImm(ThisVal);
|
||||||
|
} else {
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
|
||||||
|
.addReg(BaseReg, RegState::Kill);
|
||||||
|
}
|
||||||
|
BaseReg = DestReg;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned Chunk = ((1 << NumBits) - 1) * Scale;
|
||||||
|
while (Bytes) {
|
||||||
|
unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
|
||||||
|
Bytes -= ThisVal;
|
||||||
|
ThisVal /= Scale;
|
||||||
|
// Build the new tADD / tSUB.
|
||||||
|
if (isTwoAddr)
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
|
||||||
|
.addReg(DestReg).addImm(ThisVal);
|
||||||
|
else {
|
||||||
|
bool isKill = BaseReg != ARM::SP;
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
|
||||||
|
.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
|
||||||
|
BaseReg = DestReg;
|
||||||
|
|
||||||
|
if (Opc == ARM::tADDrSPi) {
|
||||||
|
// r4 = add sp, imm
|
||||||
|
// r4 = add r4, imm
|
||||||
|
// ...
|
||||||
|
NumBits = 8;
|
||||||
|
Scale = 1;
|
||||||
|
Chunk = ((1 << NumBits) - 1) * Scale;
|
||||||
|
Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
|
||||||
|
isTwoAddr = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ExtraOpc)
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg)
|
||||||
|
.addReg(DestReg, RegState::Kill)
|
||||||
|
.addImm(((unsigned)NumBytes) & 3);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void emitSPUpdate(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
const TargetInstrInfo &TII, DebugLoc dl,
|
||||||
|
const Thumb2RegisterInfo &MRI,
|
||||||
|
int NumBytes) {
|
||||||
|
emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
|
||||||
|
MRI, dl);
|
||||||
|
}
|
||||||
|
|
||||||
|
void Thumb2RegisterInfo::
|
||||||
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator I) const {
|
||||||
|
if (!hasReservedCallFrame(MF)) {
|
||||||
|
// If we have alloca, convert as follows:
|
||||||
|
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
|
||||||
|
// ADJCALLSTACKUP -> add, sp, sp, amount
|
||||||
|
MachineInstr *Old = I;
|
||||||
|
DebugLoc dl = Old->getDebugLoc();
|
||||||
|
unsigned Amount = Old->getOperand(0).getImm();
|
||||||
|
if (Amount != 0) {
|
||||||
|
// We need to keep the stack aligned properly. To do this, we round the
|
||||||
|
// amount of space needed for the outgoing arguments up to the next
|
||||||
|
// alignment boundary.
|
||||||
|
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
|
||||||
|
Amount = (Amount+Align-1)/Align*Align;
|
||||||
|
|
||||||
|
// Replace the pseudo instruction with a new instruction...
|
||||||
|
unsigned Opc = Old->getOpcode();
|
||||||
|
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
|
||||||
|
emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
|
||||||
|
} else {
|
||||||
|
assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
|
||||||
|
emitSPUpdate(MBB, I, TII, dl, *this, Amount);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
MBB.erase(I);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// emitThumbConstant - Emit a series of instructions to materialize a
|
||||||
|
/// constant.
|
||||||
|
static void emitThumbConstant(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
unsigned DestReg, int Imm,
|
||||||
|
const TargetInstrInfo &TII,
|
||||||
|
const Thumb2RegisterInfo& MRI,
|
||||||
|
DebugLoc dl) {
|
||||||
|
bool isSub = Imm < 0;
|
||||||
|
if (isSub) Imm = -Imm;
|
||||||
|
|
||||||
|
int Chunk = (1 << 8) - 1;
|
||||||
|
int ThisVal = (Imm > Chunk) ? Chunk : Imm;
|
||||||
|
Imm -= ThisVal;
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
|
||||||
|
if (Imm > 0)
|
||||||
|
emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
|
||||||
|
if (isSub)
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg)
|
||||||
|
.addReg(DestReg, RegState::Kill);
|
||||||
|
}
|
||||||
|
|
||||||
|
void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||||
|
int SPAdj, RegScavenger *RS) const{
|
||||||
|
unsigned i = 0;
|
||||||
|
MachineInstr &MI = *II;
|
||||||
|
MachineBasicBlock &MBB = *MI.getParent();
|
||||||
|
MachineFunction &MF = *MBB.getParent();
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
DebugLoc dl = MI.getDebugLoc();
|
||||||
|
|
||||||
|
while (!MI.getOperand(i).isFI()) {
|
||||||
|
++i;
|
||||||
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned FrameReg = ARM::SP;
|
||||||
|
int FrameIndex = MI.getOperand(i).getIndex();
|
||||||
|
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
|
||||||
|
MF.getFrameInfo()->getStackSize() + SPAdj;
|
||||||
|
|
||||||
|
if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
|
||||||
|
Offset -= AFI->getGPRCalleeSavedArea1Offset();
|
||||||
|
else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
|
||||||
|
Offset -= AFI->getGPRCalleeSavedArea2Offset();
|
||||||
|
else if (hasFP(MF)) {
|
||||||
|
assert(SPAdj == 0 && "Unexpected");
|
||||||
|
// There is alloca()'s in this function, must reference off the frame
|
||||||
|
// pointer instead.
|
||||||
|
FrameReg = getFrameRegister(MF);
|
||||||
|
Offset -= AFI->getFramePtrSpillOffset();
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned Opcode = MI.getOpcode();
|
||||||
|
const TargetInstrDesc &Desc = MI.getDesc();
|
||||||
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
||||||
|
|
||||||
|
if (Opcode == ARM::tADDrSPi) {
|
||||||
|
Offset += MI.getOperand(i+1).getImm();
|
||||||
|
|
||||||
|
// Can't use tADDrSPi if it's based off the frame pointer.
|
||||||
|
unsigned NumBits = 0;
|
||||||
|
unsigned Scale = 1;
|
||||||
|
if (FrameReg != ARM::SP) {
|
||||||
|
Opcode = ARM::tADDi3;
|
||||||
|
MI.setDesc(TII.get(ARM::tADDi3));
|
||||||
|
NumBits = 3;
|
||||||
|
} else {
|
||||||
|
NumBits = 8;
|
||||||
|
Scale = 4;
|
||||||
|
assert((Offset & 3) == 0 &&
|
||||||
|
"Thumb add/sub sp, #imm immediate must be multiple of 4!");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (Offset == 0) {
|
||||||
|
// Turn it into a move.
|
||||||
|
MI.setDesc(TII.get(ARM::tMOVhir2lor));
|
||||||
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
||||||
|
MI.RemoveOperand(i+1);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Common case: small offset, fits into instruction.
|
||||||
|
unsigned Mask = (1 << NumBits) - 1;
|
||||||
|
if (((Offset / Scale) & ~Mask) == 0) {
|
||||||
|
// Replace the FrameIndex with sp / fp
|
||||||
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
||||||
|
MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned DestReg = MI.getOperand(0).getReg();
|
||||||
|
unsigned Bytes = (Offset > 0) ? Offset : -Offset;
|
||||||
|
unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
|
||||||
|
// MI would expand into a large number of instructions. Don't try to
|
||||||
|
// simplify the immediate.
|
||||||
|
if (NumMIs > 2) {
|
||||||
|
emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
|
||||||
|
*this, dl);
|
||||||
|
MBB.erase(II);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (Offset > 0) {
|
||||||
|
// Translate r0 = add sp, imm to
|
||||||
|
// r0 = add sp, 255*4
|
||||||
|
// r0 = add r0, (imm - 255*4)
|
||||||
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
||||||
|
MI.getOperand(i+1).ChangeToImmediate(Mask);
|
||||||
|
Offset = (Offset - Mask * Scale);
|
||||||
|
MachineBasicBlock::iterator NII = next(II);
|
||||||
|
emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
|
||||||
|
*this, dl);
|
||||||
|
} else {
|
||||||
|
// Translate r0 = add sp, -imm to
|
||||||
|
// r0 = -imm (this is then translated into a series of instructons)
|
||||||
|
// r0 = add r0, sp
|
||||||
|
emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
|
||||||
|
MI.setDesc(TII.get(ARM::tADDhirr));
|
||||||
|
MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
|
||||||
|
MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
} else {
|
||||||
|
unsigned ImmIdx = 0;
|
||||||
|
int InstrOffs = 0;
|
||||||
|
unsigned NumBits = 0;
|
||||||
|
unsigned Scale = 1;
|
||||||
|
switch (AddrMode) {
|
||||||
|
case ARMII::AddrModeT1_s: {
|
||||||
|
ImmIdx = i+1;
|
||||||
|
InstrOffs = MI.getOperand(ImmIdx).getImm();
|
||||||
|
NumBits = (FrameReg == ARM::SP) ? 8 : 5;
|
||||||
|
Scale = 4;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
default:
|
||||||
|
assert(0 && "Unsupported addressing mode!");
|
||||||
|
abort();
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
Offset += InstrOffs * Scale;
|
||||||
|
assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
|
||||||
|
|
||||||
|
// Common case: small offset, fits into instruction.
|
||||||
|
MachineOperand &ImmOp = MI.getOperand(ImmIdx);
|
||||||
|
int ImmedOffset = Offset / Scale;
|
||||||
|
unsigned Mask = (1 << NumBits) - 1;
|
||||||
|
if ((unsigned)Offset <= Mask * Scale) {
|
||||||
|
// Replace the FrameIndex with sp
|
||||||
|
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
||||||
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
|
||||||
|
if (AddrMode == ARMII::AddrModeT1_s) {
|
||||||
|
// Thumb tLDRspi, tSTRspi. These will change to instructions that use
|
||||||
|
// a different base register.
|
||||||
|
NumBits = 5;
|
||||||
|
Mask = (1 << NumBits) - 1;
|
||||||
|
}
|
||||||
|
// If this is a thumb spill / restore, we will be using a constpool load to
|
||||||
|
// materialize the offset.
|
||||||
|
if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
|
||||||
|
ImmOp.ChangeToImmediate(0);
|
||||||
|
else {
|
||||||
|
// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
|
||||||
|
ImmedOffset = ImmedOffset & Mask;
|
||||||
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
||||||
|
Offset &= ~(Mask*Scale);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// If we get here, the immediate doesn't fit into the instruction. We folded
|
||||||
|
// as much as possible above, handle the rest, providing a register that is
|
||||||
|
// SP+LargeImm.
|
||||||
|
assert(Offset && "This code isn't needed if offset already handled!");
|
||||||
|
|
||||||
|
if (Desc.mayLoad()) {
|
||||||
|
// Use the destination register to materialize sp + offset.
|
||||||
|
unsigned TmpReg = MI.getOperand(0).getReg();
|
||||||
|
bool UseRR = false;
|
||||||
|
if (Opcode == ARM::tRestore) {
|
||||||
|
if (FrameReg == ARM::SP)
|
||||||
|
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
||||||
|
Offset, false, TII, *this, dl);
|
||||||
|
else {
|
||||||
|
emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
|
||||||
|
UseRR = true;
|
||||||
|
}
|
||||||
|
} else
|
||||||
|
emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
|
||||||
|
*this, dl);
|
||||||
|
MI.setDesc(TII.get(ARM::tLDR));
|
||||||
|
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
|
||||||
|
if (UseRR)
|
||||||
|
// Use [reg, reg] addrmode.
|
||||||
|
MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
|
||||||
|
else // tLDR has an extra register operand.
|
||||||
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
||||||
|
} else if (Desc.mayStore()) {
|
||||||
|
// FIXME! This is horrific!!! We need register scavenging.
|
||||||
|
// Our temporary workaround has marked r3 unavailable. Of course, r3 is
|
||||||
|
// also a ABI register so it's possible that is is the register that is
|
||||||
|
// being storing here. If that's the case, we do the following:
|
||||||
|
// r12 = r2
|
||||||
|
// Use r2 to materialize sp + offset
|
||||||
|
// str r3, r2
|
||||||
|
// r2 = r12
|
||||||
|
unsigned ValReg = MI.getOperand(0).getReg();
|
||||||
|
unsigned TmpReg = ARM::R3;
|
||||||
|
bool UseRR = false;
|
||||||
|
if (ValReg == ARM::R3) {
|
||||||
|
BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
|
||||||
|
.addReg(ARM::R2, RegState::Kill);
|
||||||
|
TmpReg = ARM::R2;
|
||||||
|
}
|
||||||
|
if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
|
||||||
|
BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
|
||||||
|
.addReg(ARM::R3, RegState::Kill);
|
||||||
|
if (Opcode == ARM::tSpill) {
|
||||||
|
if (FrameReg == ARM::SP)
|
||||||
|
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
||||||
|
Offset, false, TII, *this, dl);
|
||||||
|
else {
|
||||||
|
emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
|
||||||
|
UseRR = true;
|
||||||
|
}
|
||||||
|
} else
|
||||||
|
emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
|
||||||
|
*this, dl);
|
||||||
|
MI.setDesc(TII.get(ARM::tSTR));
|
||||||
|
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
|
||||||
|
if (UseRR) // Use [reg, reg] addrmode.
|
||||||
|
MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
|
||||||
|
else // tSTR has an extra register operand.
|
||||||
|
MI.addOperand(MachineOperand::CreateReg(0, false));
|
||||||
|
|
||||||
|
MachineBasicBlock::iterator NII = next(II);
|
||||||
|
if (ValReg == ARM::R3)
|
||||||
|
BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
|
||||||
|
.addReg(ARM::R12, RegState::Kill);
|
||||||
|
if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
|
||||||
|
BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
|
||||||
|
.addReg(ARM::R12, RegState::Kill);
|
||||||
|
} else
|
||||||
|
assert(false && "Unexpected opcode!");
|
||||||
|
}
|
||||||
|
|
||||||
|
void Thumb2RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||||
|
MachineBasicBlock &MBB = MF.front();
|
||||||
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||||
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
|
||||||
|
unsigned NumBytes = MFI->getStackSize();
|
||||||
|
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
||||||
|
DebugLoc dl = (MBBI != MBB.end() ?
|
||||||
|
MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
|
||||||
|
|
||||||
|
// Check if R3 is live in. It might have to be used as a scratch register.
|
||||||
|
for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
|
||||||
|
E = MF.getRegInfo().livein_end(); I != E; ++I) {
|
||||||
|
if (I->first == ARM::R3) {
|
||||||
|
AFI->setR3IsLiveIn(true);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
|
||||||
|
NumBytes = (NumBytes + 3) & ~3;
|
||||||
|
MFI->setStackSize(NumBytes);
|
||||||
|
|
||||||
|
// Determine the sizes of each callee-save spill areas and record which frame
|
||||||
|
// belongs to which callee-save spill areas.
|
||||||
|
unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
|
||||||
|
int FramePtrSpillFI = 0;
|
||||||
|
|
||||||
|
if (VARegSaveSize)
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
|
||||||
|
|
||||||
|
if (!AFI->hasStackFrame()) {
|
||||||
|
if (NumBytes != 0)
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
||||||
|
unsigned Reg = CSI[i].getReg();
|
||||||
|
int FI = CSI[i].getFrameIdx();
|
||||||
|
switch (Reg) {
|
||||||
|
case ARM::R4:
|
||||||
|
case ARM::R5:
|
||||||
|
case ARM::R6:
|
||||||
|
case ARM::R7:
|
||||||
|
case ARM::LR:
|
||||||
|
if (Reg == FramePtr)
|
||||||
|
FramePtrSpillFI = FI;
|
||||||
|
AFI->addGPRCalleeSavedArea1Frame(FI);
|
||||||
|
GPRCS1Size += 4;
|
||||||
|
break;
|
||||||
|
case ARM::R8:
|
||||||
|
case ARM::R9:
|
||||||
|
case ARM::R10:
|
||||||
|
case ARM::R11:
|
||||||
|
if (Reg == FramePtr)
|
||||||
|
FramePtrSpillFI = FI;
|
||||||
|
if (STI.isTargetDarwin()) {
|
||||||
|
AFI->addGPRCalleeSavedArea2Frame(FI);
|
||||||
|
GPRCS2Size += 4;
|
||||||
|
} else {
|
||||||
|
AFI->addGPRCalleeSavedArea1Frame(FI);
|
||||||
|
GPRCS1Size += 4;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
AFI->addDPRCalleeSavedAreaFrame(FI);
|
||||||
|
DPRCSSize += 8;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
|
||||||
|
++MBBI;
|
||||||
|
if (MBBI != MBB.end())
|
||||||
|
dl = MBBI->getDebugLoc();
|
||||||
|
}
|
||||||
|
|
||||||
|
// Darwin ABI requires FP to point to the stack slot that contains the
|
||||||
|
// previous FP.
|
||||||
|
if (STI.isTargetDarwin() || hasFP(MF)) {
|
||||||
|
MachineInstrBuilder MIB =
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
|
||||||
|
.addFrameIndex(FramePtrSpillFI).addImm(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Determine starting offsets of spill areas.
|
||||||
|
unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
|
||||||
|
unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
|
||||||
|
unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
|
||||||
|
AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
|
||||||
|
AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
|
||||||
|
AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
|
||||||
|
AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
|
||||||
|
|
||||||
|
NumBytes = DPRCSOffset;
|
||||||
|
if (NumBytes) {
|
||||||
|
// Insert it after all the callee-save spills.
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (STI.isTargetELF() && hasFP(MF)) {
|
||||||
|
MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
|
||||||
|
AFI->getFramePtrSpillOffset());
|
||||||
|
}
|
||||||
|
|
||||||
|
AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
|
||||||
|
AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
|
||||||
|
AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
|
||||||
|
for (unsigned i = 0; CSRegs[i]; ++i)
|
||||||
|
if (Reg == CSRegs[i])
|
||||||
|
return true;
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
|
||||||
|
return (MI->getOpcode() == ARM::tRestore &&
|
||||||
|
MI->getOperand(1).isFI() &&
|
||||||
|
isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
|
||||||
|
}
|
||||||
|
|
||||||
|
void Thumb2RegisterInfo::emitEpilogue(MachineFunction &MF,
|
||||||
|
MachineBasicBlock &MBB) const {
|
||||||
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
||||||
|
assert((MBBI->getOpcode() == ARM::tBX_RET ||
|
||||||
|
MBBI->getOpcode() == ARM::tPOP_RET) &&
|
||||||
|
"Can only insert epilog into returning blocks");
|
||||||
|
DebugLoc dl = MBBI->getDebugLoc();
|
||||||
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
|
||||||
|
int NumBytes = (int)MFI->getStackSize();
|
||||||
|
|
||||||
|
if (!AFI->hasStackFrame()) {
|
||||||
|
if (NumBytes != 0)
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
|
||||||
|
} else {
|
||||||
|
// Unwind MBBI to point to first LDR / FLDD.
|
||||||
|
const unsigned *CSRegs = getCalleeSavedRegs();
|
||||||
|
if (MBBI != MBB.begin()) {
|
||||||
|
do
|
||||||
|
--MBBI;
|
||||||
|
while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
|
||||||
|
if (!isCSRestore(MBBI, CSRegs))
|
||||||
|
++MBBI;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Move SP to start of FP callee save spill area.
|
||||||
|
NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
|
||||||
|
AFI->getGPRCalleeSavedArea2Size() +
|
||||||
|
AFI->getDPRCalleeSavedAreaSize());
|
||||||
|
|
||||||
|
if (hasFP(MF)) {
|
||||||
|
NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
|
||||||
|
// Reset SP based on frame pointer only if the stack frame extends beyond
|
||||||
|
// frame pointer stack slot or target is ELF and the function has FP.
|
||||||
|
if (NumBytes)
|
||||||
|
emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
|
||||||
|
TII, *this, dl);
|
||||||
|
else
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP)
|
||||||
|
.addReg(FramePtr);
|
||||||
|
} else {
|
||||||
|
if (MBBI->getOpcode() == ARM::tBX_RET &&
|
||||||
|
&MBB.front() != MBBI &&
|
||||||
|
prior(MBBI)->getOpcode() == ARM::tPOP) {
|
||||||
|
MachineBasicBlock::iterator PMBBI = prior(MBBI);
|
||||||
|
emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
|
||||||
|
} else
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (VARegSaveSize) {
|
||||||
|
// Epilogue for vararg functions: pop LR to R3 and branch off it.
|
||||||
|
// FIXME: Verify this is still ok when R3 is no longer being reserved.
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
|
||||||
|
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
|
||||||
|
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
|
||||||
|
MBB.erase(MBBI);
|
||||||
|
}
|
||||||
|
}
|
60
lib/Target/ARM/Thumb2RegisterInfo.h
Normal file
60
lib/Target/ARM/Thumb2RegisterInfo.h
Normal file
@ -0,0 +1,60 @@
|
|||||||
|
//===- Thumb2RegisterInfo.h - Thumb-2 Register Information Impl ----*- C++ -*-===//
|
||||||
|
//
|
||||||
|
// The LLVM Compiler Infrastructure
|
||||||
|
//
|
||||||
|
// This file is distributed under the University of Illinois Open Source
|
||||||
|
// License. See LICENSE.TXT for details.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
//
|
||||||
|
// This file contains the Thumb-2 implementation of the TargetRegisterInfo class.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
#ifndef THUMB2REGISTERINFO_H
|
||||||
|
#define THUMB2REGISTERINFO_H
|
||||||
|
|
||||||
|
#include "ARM.h"
|
||||||
|
#include "ARMRegisterInfo.h"
|
||||||
|
#include "llvm/Target/TargetRegisterInfo.h"
|
||||||
|
|
||||||
|
namespace llvm {
|
||||||
|
class ARMSubtarget;
|
||||||
|
class TargetInstrInfo;
|
||||||
|
class Type;
|
||||||
|
|
||||||
|
struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
|
||||||
|
public:
|
||||||
|
Thumb2RegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
|
||||||
|
|
||||||
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||||
|
/// specified immediate.
|
||||||
|
void emitLoadConstPool(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
unsigned DestReg, int Val,
|
||||||
|
const TargetInstrInfo *TII,
|
||||||
|
DebugLoc dl) const;
|
||||||
|
|
||||||
|
/// Code Generation virtual methods...
|
||||||
|
const TargetRegisterClass *
|
||||||
|
getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
|
||||||
|
|
||||||
|
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
|
||||||
|
|
||||||
|
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
||||||
|
|
||||||
|
bool hasReservedCallFrame(MachineFunction &MF) const;
|
||||||
|
|
||||||
|
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||||
|
MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator I) const;
|
||||||
|
|
||||||
|
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||||
|
int SPAdj, RegScavenger *RS = NULL) const;
|
||||||
|
|
||||||
|
void emitPrologue(MachineFunction &MF) const;
|
||||||
|
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
||||||
|
};
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // THUMB2REGISTERINFO_H
|
Loading…
Reference in New Issue
Block a user