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https://github.com/c64scene-ar/llvm-6502.git
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Add support for Add, Sub, And, Or, & Xor constant exprs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6049 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -203,6 +203,13 @@ namespace {
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void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
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void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
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Value *Src, const Type *DestTy, unsigned TargetReg);
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Value *Src, const Type *DestTy, unsigned TargetReg);
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/// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
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/// and constant expression support.
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void emitSimpleBinaryOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1,
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unsigned OperatorClass, unsigned TargetReg);
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/// copyConstantToRegister - Output the instructions required to put the
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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/// specified constant into the specified register.
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///
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///
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@ -314,17 +321,29 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP,
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MachineBasicBlock::iterator &IP,
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Constant *C, unsigned R) {
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Constant *C, unsigned R) {
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if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
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if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
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if (CE->getOpcode() == Instruction::GetElementPtr) {
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unsigned Class = 0;
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switch (CE->getOpcode()) {
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case Instruction::GetElementPtr:
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emitGEPOperation(MBB, IP, CE->getOperand(0),
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emitGEPOperation(MBB, IP, CE->getOperand(0),
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CE->op_begin()+1, CE->op_end(), R);
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CE->op_begin()+1, CE->op_end(), R);
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return;
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return;
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} else if (CE->getOpcode() == Instruction::Cast) {
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case Instruction::Cast:
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emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
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emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
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return;
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return;
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}
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std::cerr << "Offending expr: " << C << "\n";
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case Instruction::Xor: ++Class; // FALL THROUGH
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assert(0 && "Constant expressions not yet handled!\n");
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case Instruction::Or: ++Class; // FALL THROUGH
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case Instruction::And: ++Class; // FALL THROUGH
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case Instruction::Sub: ++Class; // FALL THROUGH
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case Instruction::Add:
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emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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Class, R);
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return;
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default:
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std::cerr << "Offending expr: " << C << "\n";
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assert(0 && "Constant expressions not yet handled!\n");
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}
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}
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}
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if (C->getType()->isIntegral()) {
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if (C->getType()->isIntegral()) {
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@ -931,13 +950,27 @@ void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
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}
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}
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/// visitSimpleBinary - Implement simple binary operators for integral types...
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/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
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/// Xor.
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void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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unsigned DestReg = getReg(B);
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MachineBasicBlock::iterator MI = BB->end();
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emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
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OperatorClass, DestReg);
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}
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/// visitSimpleBinary - Implement simple binary operators for integral types...
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/// visitSimpleBinary - Implement simple binary operators for integral types...
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/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
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/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
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/// 4 for Xor.
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/// 4 for Xor.
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///
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///
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void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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/// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
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unsigned Class = getClassB(B.getType());
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/// and constant expression support.
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void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1,
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unsigned OperatorClass,unsigned TargetReg){
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unsigned Class = getClassB(Op0->getType());
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static const unsigned OpcodeTab[][4] = {
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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// Arithmetic operators
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@ -958,17 +991,16 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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assert(Opcode && "Floating point arguments to logical inst?");
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assert(Opcode && "Floating point arguments to logical inst?");
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unsigned Op0r = getReg(B.getOperand(0));
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unsigned Op0r = getReg(Op0, BB, IP);
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unsigned Op1r = getReg(B.getOperand(1));
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unsigned Op1r = getReg(Op1, BB, IP);
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unsigned DestReg = getReg(B);
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
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BuildMI(BB, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
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if (isLong) { // Handle the upper 32 bits of long values...
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if (isLong) { // Handle the upper 32 bits of long values...
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static const unsigned TopTab[] = {
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static const unsigned TopTab[] = {
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X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
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X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
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};
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};
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BuildMI(BB, TopTab[OperatorClass], 2,
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BMI(BB, IP, TopTab[OperatorClass], 2,
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DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
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TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
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}
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}
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}
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}
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@ -203,6 +203,13 @@ namespace {
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void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
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void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
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Value *Src, const Type *DestTy, unsigned TargetReg);
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Value *Src, const Type *DestTy, unsigned TargetReg);
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/// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
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/// and constant expression support.
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void emitSimpleBinaryOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1,
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unsigned OperatorClass, unsigned TargetReg);
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/// copyConstantToRegister - Output the instructions required to put the
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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/// specified constant into the specified register.
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///
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///
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@ -314,17 +321,29 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP,
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MachineBasicBlock::iterator &IP,
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Constant *C, unsigned R) {
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Constant *C, unsigned R) {
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if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
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if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
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if (CE->getOpcode() == Instruction::GetElementPtr) {
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unsigned Class = 0;
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switch (CE->getOpcode()) {
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case Instruction::GetElementPtr:
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emitGEPOperation(MBB, IP, CE->getOperand(0),
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emitGEPOperation(MBB, IP, CE->getOperand(0),
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CE->op_begin()+1, CE->op_end(), R);
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CE->op_begin()+1, CE->op_end(), R);
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return;
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return;
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} else if (CE->getOpcode() == Instruction::Cast) {
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case Instruction::Cast:
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emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
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emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
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return;
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return;
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}
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std::cerr << "Offending expr: " << C << "\n";
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case Instruction::Xor: ++Class; // FALL THROUGH
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assert(0 && "Constant expressions not yet handled!\n");
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case Instruction::Or: ++Class; // FALL THROUGH
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case Instruction::And: ++Class; // FALL THROUGH
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case Instruction::Sub: ++Class; // FALL THROUGH
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case Instruction::Add:
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emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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Class, R);
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return;
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default:
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std::cerr << "Offending expr: " << C << "\n";
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assert(0 && "Constant expressions not yet handled!\n");
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}
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}
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}
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if (C->getType()->isIntegral()) {
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if (C->getType()->isIntegral()) {
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@ -931,13 +950,27 @@ void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
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}
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}
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/// visitSimpleBinary - Implement simple binary operators for integral types...
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/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
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/// Xor.
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void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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unsigned DestReg = getReg(B);
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MachineBasicBlock::iterator MI = BB->end();
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emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
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OperatorClass, DestReg);
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}
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/// visitSimpleBinary - Implement simple binary operators for integral types...
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/// visitSimpleBinary - Implement simple binary operators for integral types...
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/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
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/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
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/// 4 for Xor.
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/// 4 for Xor.
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///
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///
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void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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/// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
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unsigned Class = getClassB(B.getType());
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/// and constant expression support.
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void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1,
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unsigned OperatorClass,unsigned TargetReg){
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unsigned Class = getClassB(Op0->getType());
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static const unsigned OpcodeTab[][4] = {
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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// Arithmetic operators
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@ -958,17 +991,16 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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assert(Opcode && "Floating point arguments to logical inst?");
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assert(Opcode && "Floating point arguments to logical inst?");
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unsigned Op0r = getReg(B.getOperand(0));
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unsigned Op0r = getReg(Op0, BB, IP);
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unsigned Op1r = getReg(B.getOperand(1));
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unsigned Op1r = getReg(Op1, BB, IP);
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unsigned DestReg = getReg(B);
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
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BuildMI(BB, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
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if (isLong) { // Handle the upper 32 bits of long values...
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if (isLong) { // Handle the upper 32 bits of long values...
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static const unsigned TopTab[] = {
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static const unsigned TopTab[] = {
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X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
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X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
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};
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};
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BuildMI(BB, TopTab[OperatorClass], 2,
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BMI(BB, IP, TopTab[OperatorClass], 2,
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DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
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TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
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}
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}
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}
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}
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