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constify the TargetMachine being passed through the Mips subtarget

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creation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218169 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-09-19 23:30:42 +00:00
parent 784954db31
commit b53495606d
8 changed files with 18 additions and 15 deletions
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4
lib/Target/Mips/Mips16ISelLowering.cpp
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@ -120,7 +120,7 @@ static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
{"truncf", "__mips16_call_stub_sf_1"},
};
Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM,
Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
: MipsTargetLowering(TM, STI) {
@ -153,7 +153,7 @@ Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM,
}
const MipsTargetLowering *
llvm::createMips16TargetLowering(MipsTargetMachine &TM,
llvm::createMips16TargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI) {
return new Mips16TargetLowering(TM, STI);
}

2
lib/Target/Mips/Mips16ISelLowering.h
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@ -19,7 +19,7 @@
namespace llvm {
class Mips16TargetLowering : public MipsTargetLowering {
public:
explicit Mips16TargetLowering(MipsTargetMachine &TM,
explicit Mips16TargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI);
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,

4
lib/Target/Mips/MipsISelLowering.cpp
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@ -209,7 +209,7 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM,
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
: TargetLowering(TM, new MipsTargetObjectFile()), Subtarget(STI) {
// Mips does not have i1 type, so use i32 for
@ -409,7 +409,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM,
isMicroMips = Subtarget.inMicroMipsMode();
}
const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM,
const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
const MipsSubtarget &STI) {
if (STI.inMips16Mode())
return llvm::createMips16TargetLowering(TM, STI);

10
lib/Target/Mips/MipsISelLowering.h
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@ -214,10 +214,10 @@ namespace llvm {
class MipsTargetLowering : public TargetLowering {
bool isMicroMips;
public:
explicit MipsTargetLowering(MipsTargetMachine &TM,
explicit MipsTargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI);
static const MipsTargetLowering *create(MipsTargetMachine &TM,
static const MipsTargetLowering *create(const MipsTargetMachine &TM,
const MipsSubtarget &STI);
/// createFastISel - This method returns a target specific FastISel object,
@ -602,9 +602,11 @@ namespace llvm {
/// Create MipsTargetLowering objects.
const MipsTargetLowering *
createMips16TargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI);
createMips16TargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI);
const MipsTargetLowering *
createMipsSETargetLowering(MipsTargetMachine &TM, const MipsSubtarget &STI);
createMipsSETargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI);
namespace Mips {
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,

4
lib/Target/Mips/MipsSEISelLowering.cpp
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@ -35,7 +35,7 @@ static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
"stores to their single precision "
"counterparts"));
MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM,
MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI)
: MipsTargetLowering(TM, STI) {
// Set up the register classes
@ -228,7 +228,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM,
}
const MipsTargetLowering *
llvm::createMipsSETargetLowering(MipsTargetMachine &TM,
llvm::createMipsSETargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI) {
return new MipsSETargetLowering(TM, STI);
}

2
lib/Target/Mips/MipsSEISelLowering.h
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@ -20,7 +20,7 @@
namespace llvm {
class MipsSETargetLowering : public MipsTargetLowering {
public:
explicit MipsSETargetLowering(MipsTargetMachine &TM,
explicit MipsSETargetLowering(const MipsTargetMachine &TM,
const MipsSubtarget &STI);
/// \brief Enable MSA support for the given integer type and Register

2
lib/Target/Mips/MipsSubtarget.cpp
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@ -104,7 +104,7 @@ static std::string computeDataLayout(const MipsSubtarget &ST) {
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little,
MipsTargetMachine *_TM)
const MipsTargetMachine *_TM)
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),

5
lib/Target/Mips/MipsSubtarget.h
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@ -141,7 +141,7 @@ protected:
// as from the command line
enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
MipsTargetMachine *TM;
const MipsTargetMachine *TM;
Triple TargetTriple;
@ -168,7 +168,8 @@ public:
/// This constructor initializes the data members to match that
/// of the specified triple.
MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little, MipsTargetMachine *TM);
const std::string &FS, bool little,
const MipsTargetMachine *TM);
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.