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ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2153,7 +2153,7 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
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// First, split out any predication code. Ignore mnemonics we know aren't
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// predicated but do have a carry-set and so weren't caught above.
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if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
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Mnemonic != "muls") {
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Mnemonic != "muls" && Mnemonic != "smlals") {
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unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
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.Case("eq", ARMCC::EQ)
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.Case("ne", ARMCC::NE)
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@ -1403,6 +1403,20 @@ _func:
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@ CHECK: smladxhi r2, r3, r5, r8 @ encoding: [0x33,0x85,0x02,0x87]
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@------------------------------------------------------------------------------
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@ SMLAD/SMLADX
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@------------------------------------------------------------------------------
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smlal r2, r3, r5, r8
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smlals r2, r3, r5, r8
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smlaleq r2, r3, r5, r8
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smlalshi r2, r3, r5, r8
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@ CHECK: smlal r2, r3, r5, r8 @ encoding: [0x95,0x28,0xe3,0xe0]
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@ CHECK: smlals r2, r3, r5, r8 @ encoding: [0x95,0x28,0xf3,0xe0]
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@ CHECK: smlaleq r2, r3, r5, r8 @ encoding: [0x95,0x28,0xe3,0x00]
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@ CHECK: smlalshi r2, r3, r5, r8 @ encoding: [0x95,0x28,0xf3,0x80]
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@------------------------------------------------------------------------------
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@ STM*
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@------------------------------------------------------------------------------
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