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ARM assembly parsing and encoding of SMLAL instruction.

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Fix parsing of carry-setting variant SMLALS and add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-07-22 20:18:21 +00:00
parent b206daaec1
commit b544f68b70
2 changed files with 15 additions and 1 deletions
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2
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -2153,7 +2153,7 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
// First, split out any predication code. Ignore mnemonics we know aren't
// predicated but do have a carry-set and so weren't caught above.
if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
Mnemonic != "muls") {
Mnemonic != "muls" && Mnemonic != "smlals") {
unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)

14
test/MC/ARM/basic-arm-instructions.s
View File

@ -1403,6 +1403,20 @@ _func:
@ CHECK: smladxhi r2, r3, r5, r8 @ encoding: [0x33,0x85,0x02,0x87]
@------------------------------------------------------------------------------
@ SMLAD/SMLADX
@------------------------------------------------------------------------------
smlal r2, r3, r5, r8
smlals r2, r3, r5, r8
smlaleq r2, r3, r5, r8
smlalshi r2, r3, r5, r8
@ CHECK: smlal r2, r3, r5, r8 @ encoding: [0x95,0x28,0xe3,0xe0]
@ CHECK: smlals r2, r3, r5, r8 @ encoding: [0x95,0x28,0xf3,0xe0]
@ CHECK: smlaleq r2, r3, r5, r8 @ encoding: [0x95,0x28,0xe3,0x00]
@ CHECK: smlalshi r2, r3, r5, r8 @ encoding: [0x95,0x28,0xf3,0x80]
@------------------------------------------------------------------------------
@ STM*
@------------------------------------------------------------------------------